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Table 7-54 RMRR0-1 Register Bit Definitions
Name
VALID
RSVD
BASE_ADR<38:20>
RSVD
INTLV_EN
EXT_MASK
Bit(s)
Type
Function
<31>
R/W, 0
Valid. When set, the contents of this register
is valid.
<30:28>
R/W, 0
Reserved. Read as zeros.
<27:8>
R/W, 0
Base Address <39:20>. The address of Mem-
ory Channel region. Aligned to the extent size.
<7:5>
R/W, 0
Reserved. Read as zeros.
<4>
0
Memory Channel Interleave Enable. Al-
ways set to zero. Memory Channel interleave
is never enabled.
<3:0>
R/W, 0
Extent Mask. Can be used to mask the 16
least significant bits of the BASE_ADR field in
each of the Memory Channel Range registers
as follows:
<EXT_
MASK>
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Memory
Valid Base Address
Channel
Bits
Size
TLSB_ADR<39:20>
TLSB_ADR<39:21>
TLSB_ADR<39:22>
TLSB_ADR<39:23>
TLSB_ADR<39:24>
TLSB_ADR<39:25>
TLSB_ADR<39:26>
TLSB_ADR<39:27>
128 Mbytes
TLSB_ADR<39:28>
256 Mbytes
TLSB_ADR<39:29>
512 Mbytes
TLSB_ADR<39:30>
TLSB_ADR<39:31>
TLSB_ADR<39:32>
TLSB_ADR<39:33>
TLSB_ADR<39:34>
TLSB_ADR<39:35>
System Registers 7-111
1 Mbyte
2 Mbytes
4 Mbytes
8 Mbytes
16 Mbytes
32 Mbytes
64 Mbytes
1 Gbyte
2 Gbytes
4 Gbytes
8 Gbytes
16 Gbytes
32 Gbytes
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