Tldmcmd Register Bit Definitions - DEC AlphaServer 8200 Technical Manual

Table 7-33 TLDMCMD Register Bit Definitions
Name Bit(s)
<31>
DM_DONE
<30>
IN_PROG
<29:17>
RSVD
<16>
CPU_ID
RSVD <15>
<14>
RM_INTLV
<13>
RM_4
<12>
RM_3
<11>
DM_CMD_VALID
<10>
RSVD
Type Function
W1C, 0 Data Movement Done. When set, indicates that
the required function has been completed and that
the data mover is idle. This bit clears when the
CPU that initiated the data mover transaction
writes one to it. Note that when this bit is set, only
the CPU identified in TLDMCMD<CPU_ID> can
change any value in this register. Reads of this bit
by other than the CPU identified in <CPU_ID> re-
turn zero.
R, 0 Data Movement in Progress. Set when a CPU
does a write to the TLDMCMD register in which
TLDMCD0<DM_CMD_VALID> is written to a one.
Clears when the data mover has completed the
transaction specified in the register write that set
the bit. Note that if <IN_PROG> is set, reads from
the CPU that did not set TLDMCMD<IN_PROG>
receive zero response for <IN_PROG>.
R/W, 0 Reserved. Must be written as zeros.
R, 0 CPU Identification. Identifies which of the two
CPUs on the module initiated the data mover trans-
action. Set for CPU1; clear for CPU0.
R/W, 0 Reserved. Must be written as zeros.
R/W, 0 Memory Channel Interleave. When set, Mem-
ory Channel 0 is targeted (TLSB_ADR<3>), if ad-
dress bit <6> is set. When clear, Memory Channel
1 is targeted (TLSB_ADR<4>), if address bit <6> is
clear.
R/W, 0 Memory Channel Operation TLSB_ADR<4>.
When set, the normal mechanism that asserts
TLSB_ADR<4> or TLSB_ADR<3> is bypassed by
the data mover mechanism. To make data move-
ment visible to Memory Channel interfaces, one or
both of bits <13:12> of this register must be set, or
bit <14> must be set if Memory Channel interleav-
ing is enabled.
R/W, 0 Memory Channel Operation TLSB_ADR<3>.
When set, the normal mechanism that asserts
TLSB_ADR<4> or TLSB_ADR<3> is bypassed by
the data mover mechanism. To make data move-
ment visible to Memory Channel interfaces, one or
both of bits <13:12> of this register must be set, or
bit <14> must be set if Memory Channel interleav-
ing is enabled.
RTC, 0 Data Mover Command Valid. When set, indi-
cates that the data mover command is valid.
R/W, 0 Reserved. Must be written as zeros.
System Registers 7-73