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2.2.7.3
Back-to-Back Return Data
Two memory read transactions are returned back to back as follows.
TLSB_SEND_DATA for the first transaction is asserted, and the shared
and dirty state is driven to the bus. Three cycles after the first
TLSB_SEND_DATA assertion, the second memory initiates its transfer.
The two transfers proceed normally, piped three cycles apart.
2.2.7.4
Back-to-Back Return with HOLD
TLSB_HOLD is asserted in response to the first TLSB_SEND_DATA. The
timing of TLSB_HOLD is such that there is no time to prevent the second
TLSB_SEND_DATA from being sent. The second device keeps asserting
TLSB_SEND_DATA through the no-Hold cycle. TLSB_SEND_DATA is ig-
nored in any two-cycle period in which TLSB_HOLD is asserted and in the
no-Hold cycle.
2.2.7.5
CSR Data Sequencing
CSR data sequencing is similar to memory data sequencing except the
TLSB_SHARED and TLSB_DIRTY status signals are ignored. For normal
CSR transactions the slave node is responsible for data bus sequencing.
For CSR broadcast space writes the commanding node sequences the data
bus.
On CSR data transfers, the data bus transfers 32 bytes of CSR data in
each of two consecutive data cycles, beginning three cycles after the time
when TLSB_HOLD is not asserted. The timing is identical to memory
data transfers.
2.2.8 Data Bus Functions
The data bus consists of the returned data, the associated ECC bits, and
some control signals.
A TLSB data bus cycle is the time occupied by three cycles of the TLSB
clock. During the first two clock cycles the data bus signals are driven
with data. The third clock cycle is used for a tristate dead cycle. This
leads to a simpler electrical interface design and the lowest achievable
clock cycle time. There is only one cycle type on the data bus and it is the
data cycle.
2.2.8.1
Data Return Format
When a slave node is ready to transfer data, and it is its turn to use the
data bus, the device drives TLSB_SEND_DATA on the bus. Devices have
one cycle, or more than one cycle if TLSB_HOLD is asserted, to respond
with the shared and dirty state of the block.
For read transactions, if a CPU indicates that the block is dirty in its
cache, that CPU drives the data to the bus. In all other cases the slave
node drives the data. If a CPU has not yet determined the shared or dirty
state of the block in its cache, or if it knows that it is not ready to take part
in the data transfer, the CPU can drive TLSB_HOLD. TLSB_HOLD acts
as a transaction stall.
TLSB Bus 2-19
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