Tlsb Bank Match Logic; Tlsb Parity Check; Tlsb Sequence Control - DEC AlphaServer 8200 Technical Manual

command is one of the factors in determining if the command is acknowl-
edged (TLSB_CMD_ACK) by this node. Table 5-1 shows the encoding of
TLSB commands.
Table 5-1 TLSB Command Encoding
5.1.1.6

TLSB Bank Match Logic

The bank match logic compares the bank number received from the TLSB
to the virtual ID numbers located in the TLSB Virtual ID register (TL-
VID). Virtual ID A corresponds to bank 0 and Virtual ID B corresponds to
bank 1. Having a match on one of the two banks is another factor that de-
termines if the TLSB command is to be acknowledged (TLSB_CMD_ ACK)
by this node.
5.1.1.7

TLSB Parity Check

Parity is checked on the following TLSB signals:
5.1.1.8

TLSB Sequence Control

TLSB data bus transactions take place in the order in which the com-
mands are posted on the TLSB bus. Therefore, for every command/address
transaction there is an associated 4-bit sequence number that is main-
tained internally in the CTL. The node that receives a command/address
destined for it tags that transaction with the appropriate sequence num-
ber. When that tagged sequence is next on the data bus, the node issues a
TLSB_SEND_DATA indication with the sequence number on the TLSB,
TLSB_SEQ<3:0>.
The CTL keeps two sets of counters, one for address bus sequencing (in-
coming commands) and one for data bus sequencing (data return). The ad-
dress bus counter is initialized to a value of zero; therefore, the first com-
mand/address request on the TLSB will have a sequence number of zero
associated with it. This count is incremented every time a command ac-
knowledge (TLSB_CMD_ACK) is received from the TLSB bus. The data
bus sequence counter is incremented each time a TLSB_SEND_DATA is
Command
No-op
Victim
Read
Write
Read Bank Lock
Write Bank Unlock
CSR Read
CSR Write
• ADR<30:5>, covered by ADR_PAR, which is odd parity covering all 26
bits.
• CMD<3:0>, BANK_NUM<3:0>, and ADR<39:31> are covered by
CMD_BANK_PAR, which is odd parity covering all 17 bits.
Code Description
000 No operation
001 Victim eviction (as memory write)
010 Memory read
011 Memory write
100 Read memory bank, lock
101 Write memory bank, unlock
110 Read CSR data
111 Write CSR data
Memory Interface 5-3