Table of Contents
Advertisement
To facilitate the multiplexing of the 256 bits of TLSB data to the 128 bits
required by the DECchip 21164 interface, longwords (0,4), (1,5), (2,6) and
(3,7) are paired together. This pairing is achieved by "criss-crossing" the
signals coming from the TLSB connector to the DIGA pins.
The DIGA transfers CSR data to/from the ADG and data path. It contains
registers to support I/O and interprocessor interrupts, and diagnostic func-
tions. The DIGA also provides an access path to the Gbus logic and the
MMG.
3.1.5 B-Cache
The B-cache is a 4-Mbyte nonpipelined cache using 256Kx4 SRAMs.
Cache operations required to support bus activity are directed through the
DECchip 21164. The B-cache block size is 64 bytes. Each entry in the B-
cache has an associated tag entry that contains the identification tag for
the block in the cache as well as the block's status as required by the TLSB
cache coherency protocol.
A duplicate copy of the tag store is maintained to allow for TLSB coherency
checks. This is referred to as the DTag and is controlled by the ADG.
The B-cache cycle time from the DECchip 21164 is 6 CPU cycles. At a
clock rate of 3.3 ns, this translates to a 19.8 ns access time.
3.2 Console
The system console is the combined hardware/software subsystem that
controls the system at power-up or when a CPU is halted or reset. The
system console consists of the following components:
Users can access the console through the local console terminal.
This section provides an overview of the console hardware that resides on
the CPU module. The console software user interface is described in detail
in the CPU Module Console Specification. The control panel and the cabi-
net control logic are described in detail in the CCL Specification.
Each CPU module provides console hardware for use by the console pro-
gram. Major components of the console hardware include:
3-4 CPU Module
• The console program that resides and executes on each CPU module
• Console terminal
• A control panel with switches, indicators, and connectors
• Cabinet control logic that resides on its own module
• Console hardware that resides on each CPU module
• An area of FEPROM accessed as a serial ROM shared between both
DECchip 21164s
• A shared set of FEPROMs for second-level console program storage
and miscellaneous parameter/log storage
• A shared set of UARTs that allow the console program to communicate
serially with a console terminal and the system power supplies
• A watch chip that provides the time of year (TOY) and the interval
timer needed by the console program and operating system software
Advertisement
Table of Contents
