Mmg; Adg; Diga - DEC AlphaServer 8200 Technical Manual

At reset, the contents of a console FEPROM are loaded serially into the
DECchip 21164 I-cache to initiate module self-test and first-level boot-
strap. The remaining boot and test code can be accessed from the Gbus.
Refer to the DECchip 21164 Functional Specification for a detailed discus-
sion of the DECchip 21164 functions and the PALcode.

3.1.2 MMG

The MMG gate array time-multiplexes the addresses to and from both
DECchip 21164s to the interface control chip (ADG). Two half-width (18-
bit) bidirectional address paths connect the MMG to the ADG. Two full-
width (36-bit) bidirectional paths connect the MMG to the DECchip
21164s. In addition, the MMG supplies write data for the duplicate tag
store and is used to perform some Gbus addressing and sequencing func-
tions.

3.1.3 ADG

The ADG, together with the DIGA, interfaces the CPU module to the
TLSB bus. The ADG gate array contains the interface control logic for
DECchip 21164, MMG, TLSB, and DIGA. Addresses are passed by the
MMG to the ADG. Commands are communicated directly between the
DECchip 21164s and the ADG. The ADG also handles coherency checks
required by the cache coherency protocol and schedules data movement as
required to maintain coherency.

3.1.4 DIGA

The DIGA consists of four identical chips, DIGA0 to DIGA3. The DIGA
chips, together with the ADG, interface the CPU module to the TLSB bus.
The TLSB data bus is 256 bits wide with 32 associated ECC bits calculated
on a quadword basis. The DECchip 21164 interfaces support 128 bits of
data plus ECC. The DIGA supplies the 128 bits required by the cache and
CPU from the 256-bit TLSB transfer. On outgoing data moves, the DIGA
assembles the 256 bits of TLSB data. The DIGA also provides buffering
for incoming and outgoing data transfers as well as victim storage.
• On-chip 8-Kbyte virtual instruction cache with seven-bit ASNs
(MAX_ASN=127).
• On-chip dual-read-ported 8-Kbyte data cache (implemented as two 8-
Kbyte data caches containing identical data).
• On-chip write buffer with six 32-bit entries.
• On-chip 96-Kbyte 3-way set associative writeback second-level cache.
• Bus interface unit that contains logic to access an optional third-level
writeback cache without CPU module action. The size and access time
of the third-level cache are programmable.
• On-chip performance counters to measure and analyze CPU and sys-
tem performance.
• An instruction cache diagnostic interface to support chip and module-
level testing.
CPU Module 3-3