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8.2 Nonvectored Interrupts
In a nonvectored interrupt, the interrupting node writes a value to a speci-
fied location in TLSB broadcast space. The dispatch of this request is im-
plementation specific.
To post an interprocessor interrupt, a processor sets the relevant MASK
bit in the TLIPINTR register. The bits are write-one-to-set. Clearing is
implementation dependent. I/O nodes also use this register to post nonvec-
tored interrupts.
The TLIPINTR register is in TLSB broadcast space. Writes are accepted
without regard to receiver ID. All CPU nodes accept writes to this regis-
ter. Reads of the TLIPINTR register are illegal.
8.3 I/O Interrupt Mechanism
I/O subsystems field an interrupt to an I/O port by sending an interrupt
IPL level and IDENT vector up the hose. The I/O port interrupts a CPU by
posting an interrupt at a particular interrupt level to the CPU. The CPU
responds by reading the IDENT register in the I/O port to determine the
offset vector to be used in processing the interrupt. When all interrupts at
a particular level have been serviced, the IDENT register is read as zero
and the processor is passively released.
CPUs can interrupt each other by posting interrupts to the Interprocessor
Interrupt Register. Other module-level interrupt sources exist (UARTs, in-
terval timer).
8.3.1 TLSB Principles for Interrupts
Interrupt operations proceed through various steps. Registers are used to
specify the destination and other parameters of the interrupt and to direct
the interrupt through the various steps. The following registers are used
to execute the various steps in an interrupt operation:
• The targeted CPUs are interrupted at an appropriate level and the
CPU issues a CSR read transaction over the TLSB bus to the TLILIDn
register for the relevant interrupt level to get the interrupt vector.
• After the CSR read of TLILIDn is successfully completed, the I/O mod-
ule considers the interrupt to be serviced.
• If an interrupt targets more than one CPU, the first CPU to win the
TLSB for the CSR read of TLILIDn gets the relevant IDENT informa-
tion. If another interrupt at the relevant level is pending, additional
CSR reads of TLILIDn will return that IDENT information. If no
other interrupts are pending at the given level, the I/O module will re-
turn zeros, forcing the CPU to take a passive release.
• TLVID
• Interrupt registers
• Interrupt Mask registers
• Interrupt Summary registers
Interrupts 8-3
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