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Table 7-4 TLBER Register Bit Definitions (Continued)
Name
Bit(s)
<23>
DS3
DS2
<22>
<21>
DS1
<20>
DS0
<19>
CWDE2
CRDE
<18>
<17>
CWDE
Type
Function
R, U
Data Syndrome 3. A status bit set when the
TLESR3 register contains status relative to the
current data error. This bit is undefined when
CRDE, CWDE, and UDE are zero. It is over-
written on a second error of higher significance.
R, U
Data Syndrome 2. A status bit set when the
TLESR2 register contains status relative to the
current data error. This bit is undefined when
CRDE, CWDE, and UDE are zero. It is over-
written on a second error of higher significance.
R, U
Data Syndrome 1. A status bit set when the
TLESR1 register contains status relative to the
current data error. This bit is undefined when
CRDE, CWDE, and UDE are zero. It is over-
written on a second error of higher significance.
R, U
Data Syndrome 0. A status bit set when the
TLESR0 register contains status relative to the
current data error. This bit is undefined when
CRDE, CWDE and UDE are zero. It is overwrit-
ten on a second error of higher significance.
W1C, 0
Second Correctable Write Data Error. Set
when a second CWDE error is received when
<CWDE> is still set from the first error.
W1C, 0
Correctable Read Data Error. Set when a
CRECC error is set in any TLESRn register.
This is a soft error that asserts TLSB_DATA_
ERROR if CRDD is not set in the TLCNR regis-
ter.
I/O: Posts an IPL 17 error interrupt after as-
serting TLSB_DATA_ERROR if interrupts are
enabled.
W1C, 0
Correctable Write Data Error. Set when a
CWECC error is set in any TLESRn register.
This is a soft error that asserts TLSB_DATA_
ERROR if CWDD is not set in the TLCNR regis-
ter.
I/O: Posts an IPL 17 error interrupt after as-
serting TLSB_DATA_ERROR if interrupts are
enabled.
System Registers 7-9
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