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Table 7-10 TLFADRn Register Bit Definitions (Continued)
Name
Bit(s)
TLFADR1
<24>
ADRV
<23:20>
FBANK
<19>
RSVD
<18:16>
FCMD
<15:8>
RSVD
<7:0>
FADR
The TLFADRn registers are updated on the following conditions, listed in
decreasing priority:
1.
2.
3.
4.
5.
If any of the bits <ADRV>, <CMDV>, or <BANKV> are set, the registers
are considered to be latched. A second occurrence of the same update con-
dition does not overwrite latched status. However, latched status is over-
written if an update condition of higher priority occurs. The priority of
each update condition is denoted by the number in the above list. A prior-
ity of 1 is the highest priority. When latched status is overwritten by a
higher priority condition, all fields are updated, even if the update results
in clearing <ADRV>, <CMDV>, or <BANKV>.
Software may unlatch the status by writing ones to the <ADRV>,
<CMDV>, and <BANKV> bits to clear them.
The node-specific conditions include, but are not limited to, receipt of
TLSB_DATA_ERROR when the node is participating in the data transfer
(as commander or a slave). Nodes are encouraged to latch status on addi-
tional error conditions.
All nodes must latch the command and bank number for all conditions
listed above. All nodes must latch the address on address bus errors (that
is, <NAE>, <FNAE>, <APE>, <ATCE>, and TLBER<BAE>). Memory
nodes must latch the address on data bus errors.
Type
Function
W1C, 0
Address Valid. Set when <FADR> contains a valid
address from a bus transaction.
R, U
Failing Bank Number. The bank number field
from the command that resulted in an error. This
field is Undefined when <BANKV> is zero.
R0
Reserved. Reads as zero.
R, U
Failing Command Code. The command code field
from the command that resulted in an error. This
field is Undefined when <CMDV> is zero.
R0
Reserved. Read as zeros.
R, U
Failing Address<39:32>. The high-order address
field bits from the command that resulted in an er-
ror. This field is Undefined when <ADRV> is zero.
<FNAE>, <APE>, <ATCE>, or TLBER<BAE> set in TLBER register
<UDE> or <NAE> sets in TLBER register
<CWDE> sets in TLBER register
<CRDE> sets in TLBER register
Node-specific conditions
System Registers 7-25
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