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detected on the Up Hose (for example, a parity error or sequence error), or
if the TLSB bus Read-Modify-Write operation is unsuccessful, the I/O port
logs the error and generates an error interrupt to the CPU(s).
6.3.7 Extended NVRAM Write Transactions
The Memory Channel write transaction is used to deliver a block of data,
along with its TLSB physical address, to the remote I/O bus. This transac-
tion is used to support Prestoserve NVRAM writes.
Prestoserve NVRAM writes operate in an enhanced performance mode. A
section in TLSB memory may be designated as an extended NVRAM write
region.
The I/O port houses two Down Hose range register pairs. These register
pairs must be configured at system initialization. The I/O port compares
all extended NVRAM writes targeted to it against its Down Hose Range
registers. If a match occurs, the I/O port assembles the Memory Channel
write packet and transmits it to a remote I/O adapter on the targeted
Down Hose.
The Memory Channel write packet contains up to a 40-bit TLSB address
plus either 32 bytes (hexword) or 64 bytes (double hexword) of data. All
the data is written. The mapping between the TLSB address in the packet
and an address on the remote I/O bus is dependent on the I/O bus adapter.
Flow control is maintained by a pair of Memory Channel queue counters in
each TLSB commander node. Each commander node increments its associ-
ated queue counters whenever it detects a memory write on the TLSB with
TLSB_ADR<4:3> being a nonzero value.
The Memory Channel queue counters for each commander node are incre-
mented as follows:
For node 8: Increment for TLSB_ADR<3> = 1
For node 4,5,6 or 7: Increment for TLSB_ADR<4> = 1
When the I/O port empties the extended NVRAM write from its internal
buffer, it uses a CSR write command to the Memory Channel Decr Queue
Counter Register (TLRMDQRx) in the CSR broadcast space. The I/O port
does not ACK the write broadcast nor does it generate the associated Mem-
ory Channel queue counter.
For I/O Port in node 8:
TLRMDQR8 = BSB + 640
For I/O Port in node 4,5,6 or 7: TLRMDQRx = BSB + 600
The I/O port then transmits a Memory Channel write packet on the associ-
ated Down Hose if the targeted remote I/O adapter has an available buffer
to receive the packet.
The threshold of the Memory Channel queue counters is set at five. All
commander nodes must not transmit Memory Channel writes on the TLSB
if either Memory Channel queue counter exceeds a count of five. (Note
that this is an OR condition of the two counters.)
The I/O bus adapter acknowledges each Down Hose write packet with a
window write status return packet. This packet indicates the success or
failure of the write and provides flow control.
I/O Port 6-13
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