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Some errors are more important to software than others. For example,
should two correctable data errors occur, one during a write to memory
and the other during a read from memory, the error during the write
would be more important. The software can do no more than log the read
error as it should be corrected by hardware. But the memory location is
written with a single-bit data error. Software may rewrite that memory
location so every read of that location will not report an error in the future.
The priority of errors follows:
Status registers are overwritten with data only if a higher priority data er-
ror occurs. If software finds multiple data error bits set, the information in
the status registers reflects status for the highest priority error. If multi-
ple errors of the same priority occur, the information is the status registers
reflects the first of the errors.
The node-specific conditions include, but are not limited to, receipt of
TLSB_DATA_ERROR when the node participates in the data transfer (as
commander or a slave).
2.4.6 Error Recovery
The behavior of a module, in response to detection of bits set in the TLBER
register, is largely module specific. Memory modules generally take no ac-
tion. Processors take some appropriate action which may vary depending
on the type of processor and operating system, and so on.
The following subsections describe possible node behaviors and should not
be construed as requirements.
2.4.6.1
Read Errors
Read data operations involve up to three nodes. The commander issues
the command and receives the data. A memory node acknowledges as the
slave and prepares to read the data from storage and drive it on the bus.
The memory also provides the timing for the data transaction. All other
nodes check to see if the data is dirty in their cache. Only one node can
have dirty data. That node becomes the third node involved in the data
transfer by asserting TLSB_DIRTY and driving the data.
The commander knows if the data arrives with errors because error bits
are set in its TLBER register. If the data can be corrected, it is passed to
the requester. If the data cannot be corrected, the requester must be noti-
fied of the error. The CPU can determine the appropriate action to
uncorrectable read data by the mode in which the read was requested:
• <FNAE>, <APE>, <ATCE>, or <BAE> error bits in TLBER register —
highest priority
• <UDE> or <NAE> error bits in TLBER register
• <CWDE> error bit in TLBER register
• <CRDE> error bit in TLBER register
• Node-specific conditions — lowest priority
• A read in kernel mode results in crashing the system.
• A read in user mode results in the user's process being killed.
TLSB Bus 2-43
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