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MDRA—Memory Diagnostic Register A
Address
BB + 0000 1980
Access
R/W
MDRA register A is used by diagnostics and manufacturing to
force error conditions in the memory module and isolate failures.
31 30 29 28 27
RFR
Table 7-48 MDRA Register Bit Definitions
Name
Bit(s)
<31>
DRFSH
<30>
BRFSH
7-98 System Registers
RSVD
DEDA: TLSB Data Err Dis
POEMC: Pause on Err Mode Cont
POEM: Pause on Err Mode
BRFSH: Burst Refresh
DRFSH: Dis Refresh
MMPS: Moving Inv Pattern Sel
FCAPE: Force Col Addr Par Err
Type
R/W, 0
W, 0
9
FRUN: Free Run
EXST: Exec Self-Test
FRAPE: Force Row Addr Par Err
AMEN: Addr Match Ena
Function
Disable Refresh. When set, "on-board" refresh
of the module is disabled and diagnostic burst re-
fresh, bit <30>, is enabled. When this bit is set
concurrently with bit <30>, a burst refresh cycle
will be executed.
Burst Refresh. When set, and bit <31> is also
set, a single row address within the addressed
DRAMs will be refreshed as per CAS before RAS
refresh operation. When this bit is set concur-
rently with bit <31>, a burst refresh cycle is exe-
cuted.
8
7
6
5
4
3
2
1
0
BXB-0752-92
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