Table of Contents
Advertisement
Table 7-27 TLEPDERR Register Bit Definitions
Name
Bit(s)
<31:3>
RSVD
<2>
GBTO
<1>
D2DCPE0
<0>
A2DCPE
7-58 System Registers
Type
Function
R/W, 0
Reserved. Must be written as zeros.
W1C, 0
Gbus Timeout Error. Set when DIGA0 issues a
Gbus read and fails to receive Gbus Acknowledge
within the Gbus timeout period. This error indicates
that the CPU module is unable to access some Gbus re-
source. This error also results in a TLSB data timeout
error and causes assertion of TLSB_FAULT (unless
<FRIGN> is asserted). The CPU module treats this as
an error by asserting a machine check interrupt.
DECchip 21164 treats this as a synchronous error, en-
tering a machine check handler when its internal read
counter times out. This is a system fatal error.
W1C, 0
DIGA to DIGA CSR Parity Error #0. Set when
DIGA0 detects a parity error on the DIGA to DIGA
CSR bus. This error can occur when a CSR in DIGA0
is being written or read. This error can be detected on
either CSR data or CSR command/address informa-
tion, but only when the DIGA0's DCSR valid bit is as-
serted, or during a DIGA0 to DIGA0 data movement.
This error indicates that CSR data has been corrupted.
This is a hard error and causes a machine check.
W1C, 0
ADG to DIGA CSR Parity Error. Set when DIGA0
detects a parity error on the ADG to DIGA CSR bus.
This error can occur when any CPU module CSR is be-
ing read or written to. This error can be detected on
either CSR data or CSR command/address informa-
tion, but only when the ADG is driving the ACSR bus.
This error indicates that CSR data has been corrupted.
This is a hard error and causes a machine check.
Advertisement
Table of Contents
