Sparse Space Reads And Writes - DEC AlphaServer 8200 Technical Manual

Table 3-5 PCI Address Bit Descriptions
Name
IO_SPACE
IOP_SEL
HOSE
PCI_SPACE_TYP
ADDRESS
ADDRESS
3.4.4.1

Sparse Space Reads and Writes

In PCI sparse space, 128 bytes of address are mapped to one longword of
data. Data is accessible as bytes, words, tribytes, longwords, or
quadwords.
Bits <4:3> of the address do not appear on the DECchip 21164 address
bus. They must be inferred from the state of the INT4 mask bits. For
sparse reads the CPU module generates and transmits the appropriate
bits <4:3> on the TLSB_ADR bus. For writes, the entire 32-byte block of
3-12 CPU Module
Bit(s) Function
<39> DECchip 21164 I/O space if set to 1.
<38:36> Selects address space as follows:
Bits <38:36>
000
001
010
011
100
Selects hose number on that module
<35:34>
Selects PCI address space type as follows:
<33:32>
Bits <33:32>
00
01
10
11
PCI address.
<31:05>
PCI address. When bits <33:32> = 01 or 10, the length
<4:3>
decode is as follows:
Bits <4:3>
00
01
10
11
Otherwise bits <4:3> are part of the longword address.
Selected Space
Node 4
Node 5
Node 6
Node 7
Node 8
PCI Address Space Selected
Dense memory address space
Sparse I/O space address
Sparse I/O space address
Configuration space address
Length
Byte
Word
Tribyte
Longword or quadword