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Table 7-25 TLMODCONFIG Register Bit Definitions (Continued)
Name
Bit(s)
<15:13>
BQ_MAX_ENT
<12:10>
CQ_MAX_ENT
<9:6>
BCIDLETIM
<5>
RM_SIZE
<4>
LOCKOUT_EN
BCACHE_SIZE
<3:2>
<1>
CPU1_DIS
<0>
CPU0_DIS
NOTE: A write to the TLMODCONFIG register must be followed by a MEMB. The
acknowledge of this MEMB will be held off until the module is reconfig-
ured. The TLMODCONFIG register should only be written when
TLDIAG<FRIGN> is set.
Type
Function
R/W, 4
Bus Queue Maximum Entries. Indicates the maxi-
mum number of bus queue entries supported. Not all
values are supported.
R/W, 4
Cache Queue Maximum Entries. Indicates the
maximum number of cache queue entries supported.
Not all values are supported.
R/W, F
B-Cache Idle Time. Time that BC_IDLE must be as-
serted before fill data can be returned. Value indicates
the number of sysclock cycles. The default is set to the
highest value. Legal values are 2 to F. Set the value
to the desired number of cycles of BC_IDLE assertion
plus 2. (If 7 cycles of the BC_IDLE assertion are re-
quired, then set this field to 9.) The appropriate value
should be written here for optimum system perform-
ance.
R/W, F
Memory Channel Size. When set, the CPU module
sets Memory Channel threshold at five buffers; when
clear, threshold is three.
R/W, 1
Lockout Enable. When set, enables lockouts. In-
itialized to 1.
R/W, 0
B-Cache Size. Value is read by console from
GBUS$MISCR and loaded in this field. May also be
changed for prototype debug. Indicates B-cache sizes
as follows:
<BCACHE_SIZE>
00
01
10
11
CPU1 Disable. Can be set to cause service requests
R/W, 0
from the DECchip 21164 to be ignored.
CPU0 Disable. Can be set to cause service requests
R/W, 0
from the DECchip 21164 to be ignored.
Cache Size per CPU
Reserved
4 Mbytes
16 Mbytes
Reserved
System Registers 7-53
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