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Table 7-22 TLDIAG Register Bit Definitions (Continued)
Name
Bit(s)
<13>
ASRT_FLT
<12>
RSVD
<11:8>
FDE<3:0>
<7>
FDBE
<6:4>
RSVD
<3>
DTCP
DTRD
<2>
<1>
DTWR
<0>
FRIGN
7-48 System Registers
Type
Function
R/W, 0
Assert Fault. When set, clearing <FRIGN> causes
TLSB_FAULT to be asserted to the bus. On power-up re-
set, this bit is clear, as TLSB_FAULT should not be as-
serted. On node reset, self-test code sets <ASRT_FLT> to
force TLSB_FAULT assertion when <FRIGN> is cleared.
R/W, 0
Reserved. Must be written as zeros.
R/W, 0
Force Data Error. One bit assigned for each quadword.
ECC is written with a single-bit error if <FDBE> is
clear, and with a double-bit error if <FDBE> is set.
<FDE> forces an error on data being moved into the buff-
ers. These bits are provided so that the ECC error check-
ers can be tested by module diagnostics. Bad ECC is
written to the transmit buffer. Subsequent reads of this
data should detect the error. Errors are forced for as long
as the bit is set.
R/W, 0
Force Double-Bit Error. When one of the <FDE> bits
is set and this bit is clear, a single-bit error is forced onto
data transmitted to a memory space address. If this bit
is set together with one or more of the <FDE> bits,
double-bit errors are forced onto the transmitted data.
R/W, 0
Reserved. Must be written as zeros.
R/W, 0
DTag CPU. Used in conjunction with <DTWR> or
<DTRD> to specify which CPU's DTag entry is to be
tested. When DTCP is clear, DTag tests are directed at
CPU0. When DTCP is set, they are directed at CPU1.
W, 0
DTag Read. When set, causes the DTag entry associ-
ated with the next memory space read to be moved into
the TLDTAGDATA and TLDTAGSTAT registers. Valid
only when <FRIGN> is set.
W, 0
DTag Write. When set, causes the DTag entry at the in-
dex specified by the next memory space read to be writ-
ten with the value in the TLDTAGDATA and TLDTAG-
STAT registers. The entry is written to the CPU specified
by <DTCP>. Valid only when <FRIGN> is set.
R/W, 1
Force Ignore. When set, causes all TLSB transactions
to be ignored and disallows transactions from this mod-
ule to go to the TLSB. Causes the module to drop out of
the distributed arbitration scheme. <FRIGN> causes
transactions from this module to be bypassed to the bus
interface inputs without going to the bus. Note that al-
though this bit can be read, the value is read from the
copy in the DIGA chip (CPU module). Several copies of
<FRIGN> are distributed to all the control arrays.
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