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DDR0:3—Data Diagnostic Registers
Address
BB + 0001 0140; 0001 04140; 0001 8140; 0001 C140
Access
R/W
There are four DDR registers, one in each of the four MDI ASICs.
They are used by diagnostics and manufacturing to force error
conditions, to isolate failures, and to margin the DC to DC power
converters.
31
30
EFLPC: Ena Flip ECC Check Bit
MARG: Margin
Table 7-52 DDRn Register Bit Definitions
Name
Bit(s)
<31>
MARG
<30:16>
RSVD
7-106 System Registers
RSVD
EFLPD: Ena Flip Data Bit
DFLP: Data Bit to Flip
PAT: Self-Test Pattern Select
ICFR: Inhibit Clear on Free Run
CDER: Clear Self-Test Data Err Reg
Type
Function
R/W, 0
Margin. When set, margins the module's 5.0 V
and 3.35 V DC to DC converters over a +/− 5%
range.
Register
DDR0
DDR1
DDR2
DDR3
R0
Reserved. Read as zero.
13
16 15 14
9
8
7
RSVD
CFLP: Check Bit to Flip
LOE: Lock on Error
Voltage
5.0
5.0
3.5
3.5
6
4
3
2
1
0
BXB-0764-93
Margin
+5%
−5%
+5%
−5%
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