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Table 7-7 TLMMRn Register Bit Definitions (Continued)
Name
Bit(s)
<10:8>
INTLV
<7:4>
ADRMASK
<3:2>
RSVD
<1:0>
INTMASK
Table 7-8
Interleave Field Values for Two-Bank Memory Modules
Interleave
Modules
Level
Interleaved
1
2-way
4-way
2
4
8-way
8
16-way
7-22 System Registers
Type
Function
CPU, W, 0
Interleave. Lower address bits used in inter-
I/O, R/W, 0
leaving. This field is compared to physical ad-
dress lines TLSB_ADR<8:6>. Table 7-8 gives
<INTLV> values for various interleave levels.
CPU, W, 0
Address Mask. Indicates the number of ad-
I/O, R/W, 0
dress bits not used in the address comparison.
This field allows physical memory sizes from 64
Mbytes through 1 terabyte to be mapped. Ad-
dress ranges indicated by various values of
<ADRMASK> are given in Table 7-9.
CPU, W, 0
Reserved. Must be written as zero.
I/O, R/W, 0
CPU, W, 0
Interleave Mask. Indicates how many bits are
I/O, R/W, 0
valid in the interleave field. This permits 1, 2, 4,
and 8-way interleaving when <SBANK> is set,
or 2, 4, 8, and 16-way interleaving when
<SBANK> is clear. Table 7-8 gives <INTMASK>
values for various interleave levels.
<SBANK>
<INTMASK>
0
0
0
1
0
2
0
3
<INTLV>
Bank n
N/A
ADR<6>=0
0:1
ADR<7>=0
0:3
ADR<8>=0
0:7
ADR<9>=0
Bank n+8
ADR<6>=1
ADR<7>=1
ADR<8>=1
ADR<9>=1
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