Gbus$Miscr Register Bit Definitions - DEC AlphaServer 8200 Technical Manual

Table 7-37 GBUS$MISCR Register Bit Definitions
Name Bit(s)
<7>
CONWIN1R
<6>
CONWIN0R
<5>
RSVD
<4>
TLSB_RUN
<3>
TLSB_SECURE
<2>
PROCNT
CACSIZ <1:0>
7-80 System Registers
Type Function
R, 0 Console Winner CPU1 Read. When set, indi-
cates that CPU1 is running console. This is a read
copy of the write-only bit implemented in
GBUS$MISCW.
R, 0 Console Winner CPU0 Read. When set, indi-
cates that CPU0 is running console. This is a read
copy of the write-only bit implemented in
GBUS$MISCW.
R0 Reserved. Reads as zero.
R, 0 TLSB Run. A read copy of the TLSB run line, in-
dicating that some module is running an operating
system.
R, 0 TLSB Secure. Reflects the state of the
TLSB_SECURE L signal on the centerplane. This
bit is also tied to ^P DUART. When set, it inhibits
^P halts.
R, 0 Processor Count. Indicates the number of CPUs
on the module. When clear, there is one CPU pre-
sent on the module. This is always CPU0. When
set, two processors are present.
R, X B-Cache Size. Indicates the size of the B-cache.
<CACSIZ>
00
01
10
11
B-Cache Size (Mbytes)
1
4
16
Reserved