Cpu Module; Decchip 21164 - DEC AlphaServer 8200 Technical Manual

bus transactions may be overlapped, and these transactions may be over-
lapped with bus arbitration. Arbitration priority rotates in a round-robin
scheme among the nodes. A node in the slot dedicated to I/O follows a spe-
cial arbitration algorithm so that it cannot consume more than a certain
fraction of the bus bandwidth.
The TLSB supports a conditional write-update cache protocol. This proto-
col allows a node to implement a write-back cache while also offering a
very efficient method for sharing writable data. All bus data transfers are
naturally aligned, 64-byte blocks.
With this protocol, a CPU cache retains the only up-to-date copy of data.
When this data is requested, the CPU with the most recent copy returns it.
Memory ignores the transaction. Special TLSB signal lines coordinate this
operation.
The TLSB uses parity protection on the address bus. One parity bit pro-
tects the address, and one bit protects the command and other associated
fields.
The data bus is protected by ECC. An 8-bit ECC check code protects each
64 bits of data. The generator and ultimate user of the data calculate ECC
check codes, report, and correct any errors detected. TLSB bus interfaces
check (but do not correct) ECC to aid in error isolation. For example, an
I/O device calculates ECC when DMA data is written to memory. When a
CPU reads this data, the TLSB interface on the CPU module checks and
notes any errors, but the DECchip 21164 actually corrects the data prior to
using it.
The ECC check code corrects single-bit errors. It detects double-bit errors,
and some 4-bit errors, in each 64-bit unit of data.

1.3 CPU Module

The CPU module contains one or two DECchip 21164 microprocessors. In
dual-processor modules, each processor operates independently and has
its own backup cache. A single interface to the TLSB is shared by both
CPU chips. The interface to console support hardware on the CPU module
is also shared by both microprocessors. The main sections of the CPU
module are:
A simple block diagram of the CPU module is given in Chapter 3.

1.3.1 DECchip 21164

The DECchip 21164 microprocessor is a CMOS-5 (0.5 micron) superscalar,
superpipelined implementation of the Alpha architecture. A brief listing of
the DECchip 21164 features is given in Chapter 3. DECchip 21164 imple-
ments the Alpha architecture together with its associated PALcode. Refer
• DECchip 21164
• Backup cache
• TLSB interface
• Console support hardware
Overview 1-3