Interrupt Transactions; I/O Adapter To Memory Write Types - DEC AlphaServer 8200 Technical Manual

Modify-Write on the TLSB. The quadword of data that the I/O device
sends in the masked write command contains the original data with the
correct state of the lock bit, that is, bit <0> is clear.
NOTE: There is no support for interlocked commands on the Futurebus+.
DMA Unmasked Write Transactions
The I/O port supports unmasked double hexword writes to memory. Un-
masked writes map directly to block (64-byte) writes on the TLSB.
DMA Masked Write Transactions
The I/O port supports masked octaword, masked hexword, and masked
double hexword writes to memory. The Read-Modify-Write sequence exe-
cuted by the I/O port for DMA masked write transactions is an atomic op-
eration between the I/O port and TLSB memory.
This operation is guaranteed to be atomic due to the TLSB memory archi-
tecture and two new TLSB bus commands. The Read Bank Lock command
prevents access to the memory bank until the Write Bank Unlock com-
mand is issued to put the modified data back in memory. It is impossible
for another node (that is, a CPU or another I/O port) to access that memory
bank anytime between the I/O port's Read Bank Lock of the memory loca-
tion and the completion of the Write Bank Unlock back to memory. The
Read Bank Lock command locks the bank by causing the memory to keep
TLSB_BANK_AVL<n> deasserted for that bank until the Write Bank Un-
lock command is completed.
Table 6-9 summarizes the types of writes from the I/O bus adapters sup-
ported by the I/O port and the corresponding TLSB transaction(s) per-
formed in response to the hose write packet.
Table 6-9

I/O Adapter to Memory Write Types

Transaction Length
Octaword
Hexword
Double hexword
Double hexword
6.5.1.2

Interrupt Transactions

The I/O port uses CSR write transactions to perform the interrupt func-
tion. First, the I/O port looks up the CPU interrupt mask bits stored in the
TLCPUMASK register. By taking the CPU interrupt mask bits and the
IPL level of the interrupt to be posted, the data to be used for the CSR
write transaction is generated. The I/O port arbitrates for access to the
TLSB, then drives the interrupt destination mask and IPL (CPU mask and
interrupt level) onto the data bus for the first data cycle of the CSR write
transaction in broadcast space. This data is written into the TLIOINTRx
register. Which TLIOINTRx register is written is determined by the node
number of the I/O port module. A node 4 module writes to TLIOINTR4,
6-26 I/O Port
Type TLSB Transaction(s)
Masked Read Bank Lock (modify) then Write Bank Unlock
Masked Read Bank Lock (modify) then Write Bank Unlock
Masked Read Bank Lock (modify) then Write Bank Unlock
Unmasked Write