Dma Read Data Return Packet With Error; Dma Read Data Return Packet With Error Description - DEC AlphaServer 8200 Technical Manual

DMA Read Data Return packet with the error bit set is returned across the
Down Hose.
Figure 6-16

DMA Read Data Return Packet with Error

Clock cycle
31
TAG <7:0>
1
Table 6-17 gives the description of the DMA Read Data Return packet with
error.
Table 6-17 DMA Read Data Return Packet with Error Description
Field Description
The TAG<7:0> associates the DMA Read Data Return with the correspond-
Clock 1, <31:24>
ing DMA Read packet on the Up Hose. The tag is generated by the I/O bus
adapter and sent to the I/O port as part of a DMA Read packet.
The Error bit. Set if an error has been detected on this packet.
Clock 1, <23>
Are always zero.
Clock 1, <22:14>
DND<13:12> of the first cycle of a DMA Read Data Return packet is driven
Clock 1, <13:12>
with a 01 binary by the I/O port to indicate the packet type to the I/O
adapter.
Is always zero.
Clock 1, <11>
The length field indicates the length of an error free DMA Read Data Re-
Clock 1, <10:8>
turn packet. It has no meaning for this packet.
Are always zero.
Clock 1, <7:0>
INTR/IDENT Status Return Packet
The INTR/IDENT Status Return packet returns the status for an
INTR/IDENT packet previously transmitted on the Up Hose. The
INTR/IDENT Status Return packet is a flow control message. Receipt of
an INTR/IDENT Status Return packet by an I/O bus adapter allows the
I/O bus adapter to issue another INTR/IDENT packet to the I/O port at
the IPL returned in the INTR/IDENT Status Return packet.
If the I/O port detects an error while trying to process an INTR/IDENT
packet, it logs the error and generates an error interrupt to the CPU. An
INTR/IDENT Status Return packet is sent across the Down Hose so the
I/O bus adapter can still clear its INTR pending bit, if not prohibited by
the error condition. Any hose or Turbo Vortex errors detected by the I/O
port prevents the I/O port from returning an INTR/IDENT Status Return
packet. If the CSR write to the TLIOINTR register in TLSB broadcast
space (to post the interrupt to the CPU) fails, or if the C/A cycle of the CPU
read of the I/O port's TLILID register has a parity error, the I/O port does
6-44 I/O Port
DND <31:0>
24 23 22
E 0 0 0 0 0 0 0 0 0 0 1 0
14 13 12 11 10 8 7
LEN 0 0 0 0 0 0 0 0
0
BXB-0642-93