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Table 7-31 TLINTRSUM Register Bit Definitions (Continued)
Name
Bit(s)
<11:7>
IPL14_INTR
<6>
INTIM_INTR
<5>
IP_INTR
<4>
IPL17_INTR
<3>
IPL16_INTR
<2>
IPL15_INTR
IPL14_INTR
<1>
<0>
DUART0_INTR
Type
Function
R, 0
IPL14 Interrupts. Indicator of outstanding inter-
rupts at IPL14. If a bit is set in this field, it indicates
that there is at least one interrupt outstanding at
IPL17 from the node number associated with the bit.
IPL14_INTR Bit
<11>
<10>
<9>
<8>
<7>
Interval Timer Interrupt. The interval timer can be
W1C, 0
set to interrupt or to be polled. If the timer is set to
interrupt, the interrupts can be directed to either CPU
or to both. The interval timer interrupt period is the
same for both CPUs. The interrupt line from the watch
chip is cleared by reading the CSRC register in the
watch chip. The interrupt in the TLINTRSUM regis-
ter is latched and is a W1C bit. This enables both
CPUs to have interval timer interrupts enabled, and
provides a means for both CPUs to have visibility of
the interrupt source.
Interprocessor Interrupt. A write of this register
W1C, 0
with this bit set causes the interprocessor interrupt to
be cleared.
IPL17 Interrupt. Logical OR of all the IPL17 bits.
R, 0
IPL16 Interrupt. Logical OR of all the IPL16 bits.
R, 0
IPL15 Interrupt. Logical OR of all the IPL15 bits.
R, 0
IPL14 Interrupt. Logical OR of all the IPL14 bits.
R, 0
DUART0 Interrupt.
W1C, 0
Node Number
8
7
6
5
4
System Registers 7-67
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