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Table 7-26 TLEPAERR Register Bit Definitions (Continued)
Name
Bit(s)
<3>
M2AAPE1
<2>
M2AAPE0
<1>
E2MAPE1
<0>
E2MAPE0
7-56 System Registers
Type
Function
W1C, 0
MMG to ADG Address Parity Error #1. Set when
the ADG detects a parity error on the address bus be-
tween CPU1 MMG and the ADG. A parity check is
performed after the ADG has assembled the CPU ad-
dress and cmd/addr parity, as piped from the MMG,
and combined it with the CPU command sent directly
from the CPU. This error can occur at any time when
CPU1 is driving CPU1 ADDR<39:4>, CMD<3:0>, and
ADDR_CMD_PAR. This is a hard error.
W1C, 0
MMG to ADG Address Parity Error #0. Set when
the ADG detects a parity error on the address bus be-
tween CPU0 MMG and the ADG. A parity check is
performed after the ADG has assembled the CPU ad-
dress and cmd/addr parity, as piped from the MMG,
and combined it with the CPU command sent directly
from the CPU. This error can occur at any time when
CPU0 is driving CPU0 ADDR<39:4>, CMD<3:0>, and
ADDR_CMD_PAR. This is a hard error.
W1C, 0
CPU to MMG Address Parity Error #1. Set when
the ADG detects a parity error on the address bus be-
tween CPU1 and the MMG. The parity check for this
error is done in the MMG. The results are piped to the
ADG. This error can only occur when CPU1 is driving
CPU1 ADDR<39:4>, CMD<3:0>, and
ADDR_CMD_PAR. This is a hard error.
W1C, 0
CPU to MMG Address Parity Error #0. Set when
the ADG detects a parity error on the address bus be-
tween CPU0 and the MMG. The parity check for this
error is done in the MMG. The results are piped to the
ADG. This error can only occur when CPU0 is driving
CPU0 ADDR<39:4>, CMD<3:0>, and
ADDR_CMD_PAR. This is a hard error.
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