Table of Contents
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Memory mapping register error, 3-18, 6-71
Memory Mapping Register Error bit, 7-10
memory module capacity, 7-105
Memory module, overview, 1-4
Memory organization, 4-13
Memory refresh, 4-16
Memory sections, 4-10
Memory self-test, 4-16
Memory self-test error registers, 4-18
Memory space, 3-7
Memory specific registers, 7-85
Memory transactions, 4-16
Memory, main, 4-9
Merge register, 5-17
MER register, 7-97
Minimum latency mode, 6-31
MIR register, 7-87
MMG Error register, 7-59
MMG to ADG Addr Par Err #0, 7-56
MMG to ADG Addr Par Err #1, 7-56
MMPS, 7-100
MMRE, 7-10
MNFG_MODE_L, 7-77
Module transactions, 2-12
Module-level interrupts, 8-6
Moving Inversion Pattern Select bit, 7-100
Multiple data bus errors, 6-74
Multiple errors, 3-19
Multiple Error Interrupt bit, 7-120
Multiple error priority rules, 3-19
MULT_INTR_ERR, 7-120
M2AAPE0, 7-56
M2AAPE1, 7-56
N
NAE, 7-11
Node base addresses, 2-28
Node ID bits, 7-17
Node Reset bit, 7-15
Node Reset Status bit, 7-60
Node space base addresses, 7-3
Node 8 arbitration, 6-31
NODE_ID, 7-17
Nonvectored interrupts, 8-3
No acknowledge errors, 3-18, 6-71
No Acknowledge Error bit, 7-11
No Acknowledgment bits, 7-55
No acknowledgment errors, 6-71
NO_ACK, 7-55
NRST, 7-15
NVRAM daughter card, 6-83
NVRAM registers, 7-142
O
Online exercisers, 1-8
OpenVMS, 1-7
Operation completion status, 7-34
OPTION, 7-91
Option Installed bit, 7-91
P
Packet specifications, Down Hose, 6-39
Packet specifications, Up Hose, 6-52
Packet types, 6-35
PALcode, 3-2, 3-3
PAT, 7-107
Pause on Error Mode bit, 7-100
Pause on Error Mode Continue bit, 7-99
PCIA registers, 7-142
PCI accesses, 3-11
PCI address bit descriptions, 3-12
PCI device registers, 7-142
PCI interface, 6-81
PCI interrupt priority, 6-85
PCI programmer's address, 3-11
PCI_SPACE_TYP, 3-12
Physical address space map, 3-6
Physical node ID, 2-5
PIUA, 7-83
PIUA Status bit, 7-83
PIUB, 7-83
PIUB Status bit, 7-83
POEM, 7-93, 7-95, 7-100
POEMC, 7-93, 7-99
Processor Count bit, 7-80
PROCNT, 7-80
Q
Quadword Valid Enable bit, 7-47
R
RBADR, 7-33
RCV_DATA, 7-84
RCV_SDAT, 7-86, 7-141
RDATA, 7-34
Read data, 7-34
Read data buffers, 5-11
Read data output logic, 5-11
Read data path ECC algorithm, 5-11
Read-Modify-Write, 6-33
READ_DATA, 7-41
Receive Data bit, 7-84
Receive Serial Data bit, 7-86, 7-141
Refresh, 4-16
Refresh Rate bits, 7-99
Register
ADG Error, 7-54
Console Communications, 7-68
CPU Interrupt Mask, 7-31
Index-9
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