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Refer to Chapter 7 for the format of all registers used in the interrupt op-
eration.
8.3.1.1
Virtual Node Identification - TLVID
TLSB system functionality requires that certain units be identified
uniquely, independent of physical location in the system. Specifically, indi-
vidual memory banks and CPUs must be uniquely addressable entities at
the system level, independent of their physical node ID. A physical node
ID (NID) is insufficient to uniquely address a destination element when
multiple memory banks and multiple CPUs are permitted to coexist on a
module. The system employs software generated and dynamically stored
virtual node IDs in each uniquely identifiable unit. Both CPUs on a mod-
ule are considered to be uniquely identifiable units.
The console sets the virtual node IDs (VID) by writing the TLVID register
fields with the required values at power-up.
The mapping of TLVID entries to CPUs is as follows: Each DECchip
21164 on the module is identified by number. The DECchip 21164 nearest
the TLSB connector is labeled CPU0. This is the DECchip 21164 in a uni-
processor implementation. The second DECchip 21164 is labeled CPU1.
The processor identified by position on the module as CPU0 is assigned
VID A. The processor identified as CPU1 is assigned VID B. A uniproces-
sor module has VID A assigned to the single processor. Writes to VID B do
not affect module performance. Reads of VID B return the value written
previously.
8.3.1.2
Directing Interrupts - TLCPUMASK
In a multiprocessor system, interrupts can be directed to individual CPUs.
Each I/O port can be set up so that interrupts are targeted at individual or
multiple CPUs by setting the appropriate bits in the TLCPUMASK regis-
ter. For example, if bit <0> is set, interrupts can be targeted at the CPU
with VID=0.
The CPU module implements another mask in a TLINTRMASK register
which allows selective enabling and disabling of interrupts at each of the
four levels.
8.3.1.3
Directing Interrupts - TLINTRMASK
The TLINTRMASK registers allow interrupts at different IPLs to be en-
abled for each of the CPUs on a CPU module. One mask register is pro-
vided per CPU. In addition, these registers are used to enable module
level interrupts (DUART, interval timer, Ctrl/P Halt) to the CPUs. A bit
set in the mask register allows interrupts of the type corresponding to the
bit to be issued to the corresponding DECchip 21164.
8.3.1.4
Interrupt Registers - TLIOINTR4–8
I/O ports are restricted to slots 4 through 8. Based on its physical node ID,
an I/O port writes interrupts only to the corresponding TLIOINTRn inter-
rupt register. Five TLIOINTR registers are specified in the system for this
purpose. For example, interrupts from an I/O port in slot 4 are written
8-4 Interrupts
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