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are reported to DECchip 21164 through system machine check interrupts
(IPL 1F hex - SYS_MCH_CHK_IRQ). The interrupt causes the DECchip
21164 to vector to the SCB system machine check entry point (offset 660
hex) when DECchip 21164's IPL drops below 1F hex and DECchip 21164 is
not in PAL mode.
Hard errors may be either data or address related. The detection of data
related hard errors causes the CPU module to assert TLSB_DATA_ERR-
OR. The detection of the other hard errors has no effect on TLSB_DATA_-
ERROR.
Hard errors include:
3.5.1.3
Faults
This class of errors includes hard failures that compromise the operation of
a CPU module or the TLSB and preclude either a CPU module or the
TLSB from continuing operation. In the event of a fault class error, either
the DECchip 21164 or the TLSB may be incapable of completing com-
mands issued from DECchip 21164, causing DECchip 21164 and/or the
TLSB to hang. The response to a fault must, therefore, reset all TLSB
nodes and CPU DECchip 21164s to an extent that allows the DECchip
21164s to attempt an error log and orderly crash.
When a CPU module detects a fault class error, it asserts TLSB_FAULT.
In response to any assertion of TLSB_FAULT (including its own), the CPU
module reports an error to the DECchip 21164 through the CFAIL wire
(when CFAIL is asserted without CACK, DECchip 21164 interprets CFAIL
as an unmasked machine check flag). A CFAIL machine check causes the
DECchip 21164 to reset much of its cache subsystem and external inter-
face and vector to the SCB system machine check entry point (offset 660
hex) immediately, regardless of the DECchip 21164's current IPL.
Faults include:
• Uncorrectable Data Error (UDE)
• No Acknowledge Error (NAE)
• System Address Error (SYSAERR)
• System Data Error (SYSDERR)
• Duplicate Tag Data Parity Error (DTDPE)
• Duplicate Tag Status Parity Error (DTSPE)
• ADG to DIGA CSR Parity Error (A2DCPE)
• DIGA to ADG CSR Parity Error (D2ACPE)
• DIGA to DIGA CSR Parity Error #0 (D2DCPE0)
• DIGA to DIGA CSR Parity Error #1 (D2DCPE1)
• DIGA to DIGA CSR Parity Error #2 (D2DCPE2)
• DIGA to DIGA CSR Parity Error #3 (D2DCPE3)
• DIGA to MMG CSR Parity Error (D2MCPE)
• ADG to MMG Address Parity Error (A2MAPE)
• Gbus Timeout (GBTO)
CPU Module 3-15
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