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2.4.4.1
Single-Bit ECC Errors
A single-bit error on a memory data transfer is detected by a node's ECC
checking logic. The decision to correct the data or not is implementation
specific. If a node detects a single-bit ECC error, it logs the error in the
TLESRn register by setting either <CRECC> or <CWECC>, depending on
whether a read or write command failed. If a memory node detects an ECC
error in a memory lookup, the memory flags the error by also setting
<CRECC>.
A single-bit error on a CSR data transfer is treated the same way except
when the data is being written into a register and the node has no way to
correct the data. In this case, the <UECC> error bit is set.
A CRECC error sets <CRDE> in the TLBER register. A CWECC error sets
<CWDE> in the TLBER register.
When a node detects a single-bit data error, it asserts TLSB_DATA_ ER-
ROR to signal the other nodes of the error. The signaling is disabled if the
interrupt disable bit is set in the TLCNR register. Two interrupt disable
bits are used, allowing independent control of the signaling for read and
write commands.
2.4.4.2
Double-Bit ECC Errors
A double-bit error on a data transfer is detected by a node's ECC checking
logic. The error is logged in the TLESRn register by setting <UECC>. If a
memory node detects a double-bit error in a memory lookup, the memory
passes the data and ECC directly to the bus. It sets its own <UECC> error
bit to reflect the error. A UECC error sets TLBER<UDE> and the node
asserts TLSB_DATA_ERROR.
2.4.4.3
Illegal Sequence Errors
An illegal sequence error occurs when the bus sequence value that is re-
ceived with TLSB_SEND_DATA is different from the expected sequence
number. The occurrence of this error is system fatal and the
TLSB_FAULT signal is asserted four cycles after TLSB_SEND_DATA.
The <SEQE> bit is set in the TLBER register.
2.4.4.4
SEND_DATA Timeout Errors
When a data bus sequence slot is reached and a slave is expected to se-
quence the data bus, a timeout count begins. If TLSB_SEND_DATA has
not been received for 256 cycles, then a DTO error is logged in the TLBER
of the commanding node. This results in the assertion of TLSB_FAULT.
The commander node must activate the timer while waiting for
TLSB_SEND_DATA. Other nodes are not required to activate a timer, but
may do so.
It is the responsibility of the slave node to assure that the data bus is se-
quenced before the 256 cycle timeout. A node may assert
TLSB_SEND_DATA and then assert TLSB_HOLD if a longer time is
needed.
2-40 TLSB Bus
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