Memory Bank Address Decoding; Interleave Field Values For Two-Bank Memory Modules - DEC AlphaServer 8200 Technical Manual

2.2.3.3

Memory Bank Address Decoding

The minimum bank size for the TLSB address decode scheme is 64
Mbytes.
To address memory, a CPU or I/O node must perform a memory bank de-
code to test the status of the bank. The memory modules transmit the
status of each bank on the 16 TLSB_BANK_AVL lines. This permits a
node to sense the state of the bank from the bus. The TLSB early arbitra-
tion scheme allows a node to request the bus before the bank decode takes
place. If the bank is busy, or the previous address bus command made the
bank busy, the command will be nulled if the address bus is granted. If
the requester does not win the arbitration, the request is dropped. On the
TLSB the CPU or I/O node must decode the bank address prior to issuing
the command.
Each address bus commander (CPU or I/O) must implement the eight
memory mapping registers named TLMMRn, where n is in the range 0–7.
Each register decodes the bank number n, and may optionally decode the
bank number n+8. A total of 16 bank numbers can be decoded using these
eight registers. The bank decode registers are loaded by the console at
power-up after the memory configuration has been determined. See Chap-
ter 7 for the description of the TLMMRn registers.
Since each memory module contains two banks, a single TLMMRn register
can be used for decoding bank numbers. Table 2-3 shows the values for
SBANK, INTMASK, and INTLV fields of the TLMMRn register.
Table 2-3

Interleave Field Values for Two-Bank Memory Modules

Number of
Interleave Modules
Level Interleaved
1
2-way
2
4-way
8-way 4
8
16-way
Figure 2-2 shows the address decode process.
TLMMRn
TLMMRn <INT-
<SBANK> MASK>
0 0
0 1
0 2
0 3
TLMMRn
<INTLV> Bank n
Not applicable ADR<6>=0
<0:1> ADR<7>=0
<0:3> ADR<8>=0
<0:7> ADR<9>=0
Bank n+8
ADR<6>=1
ADR<7>=1
ADR<8>=1
ADR<9>=1
TLSB Bus 2-9