Dense Space Reads And Writes; Valid Values For Address Bits <6:5 - DEC AlphaServer 8200 Technical Manual

data issued by DECchip 21164 is transmitted on the TLSB, along with all
the INT4 mask bits. The I/O port pulls the appropriate longword out of the
32-byte block and packages it, along with address bits <4:3>, into a Down
Hose packet. Note that on sparse writes, the I/O port generates the <4:3>
value. These bits are driven as 00 by the CPU module.
The appropriate longword is selected by the state of bits <4:3>. If 00, the
first longword; if 01, the third longword; if 10, the fifth longword; if 11, the
seventh longword (counting from 1). This is a result of how DECchip
21164 merges the writes into its 32-byte merge buffer and of the address
bits chosen. Note that if multiple writes are done to the same PCI byte
address but with different length encodings, the largest length encoding
will be used.
For reads, the address is transmitted to the I/O port in the same way. The
I/O port creates a read Down Hose packet, sending down bits <4:3> of the
address. The PCI interface performs the transaction and returns the re-
quested data to the I/O port. The I/O port aligns the data into the proper
longword using bits <4:3>. The I/O port then does a CSR write to its data
return register and returns the data.
Sparse addresses must be natually aligned according to TLSB_ADR<6:5>.
Valid values for address bits <6:5> and corresponding data lengths ac-
cessed are given in Table 3-6.
Table 3-6 Valid Values for Address Bits <6:5>
3.4.4.2

Dense Space Reads and Writes

The entire 32-byte block is sent, along with the 32-byte aligned address, to
the I/O port. The eight INT4 mask bits are also transmitted with the data.
The I/O port converts this data into a Down Hose packet. The eight INT4
mask bits are converted into 32-byte enable bits and are included in the
packet. When the I/O port has successfully transmitted the packet down
the hose, the I/O port does a broadcast space write to its TLWSDQRn reg-
ister. This frees the CPU module to do another write.
For reads, the 32-byte aligned address is transmitted to the I/O port, which
sends it down the hose. There are no mask bits needed in this case. The
PCI interface reads 32 bytes of data from the targeted device and sends it
back up the hose. The I/O port does a broadcast space write to a special
address (the same as for the sparse space read case above). The CPU mod-
ule retrieves the data from the TLSB and presents it to the DECchip
21164. Note that the DECchip 21164 may have merged more than one
read before emitting the read command, so all 32 bytes of data must be
presented to DECchip 21164. DECchip 21164 sorts out which data to keep
and which to discard.
TLSB_ADR<6:5> Value
0, 1, 2, 3
0, 2
0, 1
0
3
Accessed Data Length
Byte
Word
Tribyte
Longword
Quadword
CPU Module 3-13