Stair Register Bit Correspondence Of Memory Address Segments - DEC AlphaServer 8200 Technical Manual

Table 7-45 STAIR Register Bit Correspondence of Memory Address Segments
Bit Set Failing Address Range
0000 0000 – 03FF FFFF
0
0400 0000 – 07FF FFFF
1
0800 0000 – 0BFF FFFF
2
0C00 0000 – 0FFF FFFF
3
4 1000 0000 – 13FF FFFF
1400 0000 – 17FF FFFF
5
1800 0000 – 1BFF FFFF
6
1C00 0000 – 1FFF FFFF
7
2000 0000 – 23FF FFFF
8
9 2400 0000 – 27FF FFFF
2800 0000 – 2BFF FFFF
10
2C00 0000 – 2FFF FFFF
11
3000 0000 – 33FF FFFF
12
3400 0000 – 37FF FFFF
13
3800 0000 – 3BFF FFFF
14
15 3C00 0000 – 3FFF FFFF
Each module executes self-test as if it were the only memory module in the
system (no interleave with other modules).
Assuming a given processor takes approximately 600 nanoseconds to scan
each 64-byte block of memory for uncorrectable ECC errors, a 64-Mbyte
failing address segment (1 meg 64-byte blocks, with failures in each block)
can be scanned from first to last block in about 600 milliseconds.
7-94 System Registers
Bit Set Failing Address Range
16 4000 0000 – 43FF FFFF
17 4400 0000 – 47FF FFFF
18 4800 0000 – 4BFF FFFF
19 4C00 0000 – 4FFF FFFF
20 5000 0000 – 53FF FFFF
21 5400 0000 – 57FF FFFF
22 5800 0000 – 5BFF FFFF
23 5C00 0000 – 5FFF FFFF
24 6000 0000 – 63FF FFFF
25 6400 0000 – 67FF FFFF
26 6800 0000 – 6BFF FFFF
27 6C00 0000 – 6FFF FFFF
28 7000 0000 – 73FF FFFF
29 7400 0000 – 77FF FFFF
30 7800 0000 – 7BFF FFFF
31 7C00 0000 – 7FFF FFFF