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only to TLIOINTR4. Interrupts at the IPL level(s) specified in bits
<19:16> are targeted at the VIDs specified in bits <15:0> (see Chapter 7).
8.3.2 Generating Interrupts
The TLCPUMASK for each I/O port and the TLINTRMASK for each CPU
are set up by the console. To generate an interrupt, the I/O port issues a
write to its corresponding TLIOINTRn register in TLSB broadcast space.
Based on whether its VID is enabled, and whether the IPL levels are en-
abled for the targeted CPU(s), the interrupt is accepted by the DIGA. If
the interrupt is targeted at a CPU on this module, then the DIGA incre-
ments the outstanding interrupt count at the posted IPL level, for the
source I/O port, for the targeted CPU, and asserts the appropriate inter-
rupt flag. The interrupt flag is then sent to the DECchip 21164 over one of
the IRQ<3:0> lines.
The CPU reads the TLILIDx register of the appropriate I/O port, at the ap-
propriate IPL level, to determine the offset vector to be used in servicing
the interrupt. The interrupt service PALcode reads the TLINTRSUM reg-
ister to determine which I/O port device is interrupting. Reads of the
TLILDx register cause the CPU module's outstanding interrupt count to be
decremented for the target I/O port, at that IPL level.
8.3.3 Servicing Interrupts
To allow a CPU to distinguish between different interrupt sources at the
same IPL, and to identify the source of interrupts it receives, PALcode
reads the TLINTRSUM register associated with the CPU. Bits <26:7> of
TLINTRSUM are used to summarize interrupts from the various I/O de-
vices.
NOTE: In addition to I/O interrupts, the CPU must be able to handle interrupts
from other CPUs and from on-module interrupt sources.
When an interrupt is posted, the targeted CPU is identified by virtual node
ID. The DIGA selects the appropriate fields from the TLIOINTRn register
based on virtual node ID for both CPUs, the TLCPUMASK and the module
specific mask register TLINTRMASK. A count is maintained of how many
interrupts are received at each level from each I/O port for each CPU. Bits
<4:1> are a logical OR of the interrupts for each of the IPL levels. These
are provided as a convenience for PALcode. Up to four interrupts at IPL
14 (hex), 15 (hex), and 16 (hex) are held for each CPU for each of the five
I/O slots. Five interrupts are stored at IPL 17 (hex) for each CPU for each
of the five I/O slots. Therefore, the CPU module is capable of queuing 85
interrupts for each of the DECchip 21164s.
8.3.4 Interprocessor Interrupts
Interrupts can also be posted from one CPU to one or more other CPUs.
Interprocessor interrupts are posted by writing the TLIPINTR register
which is in broadcast space. Interprocessor interrupts to a CPU on a given
module can be disabled by clearing <IP_ENA> in the appropriate TLINTR-
MASK register.
To post an interrupt to the CPU with VID0, bit <0> of the TLIPINTR is
set. To post an interrupt to the CPU with VID1, bit <1> of the TLIPINTR
is set, and so on. The DIGA selects the appropriate bit from the
Interrupts 8-5
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