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TLBER—Bus Error Register
Address
BB + 0040
Access
R/W
The TLBER register contains bits that are set when a TLSB node
detects errors in the TLSB system. The entire register is locked
when the first error bit gets set in this register if TLCNR<LOFE> is
set. All bits except the four DSn bits cause the register to be
locked. When the register is locked, no bits change value until all
bits are cleared by software or TLCNR<LOFE> is cleared. Locking
the register is intended only for diagnostics. Not intended for use
in normal operation.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
Fatal Data Errors
FDTCE: Fatal Data Transmit Ck Err
DCTCE: Data Control Transmit Ck Err
SEQE: Sequence Err
DSE: Data Status Err
DTO: Data Timeout
11 10
9
8
RSVD
Data Errors
UDE:
Uncorrectable
CWDE:
Correctable Write
CRDE:
Correctable Read
CWDE2
Status
DS0: Data Synd 0
DS1: Data Synd 1
DS2: Data Synd 2
DS3: Data Synd 3
DTDE: Data Transmitter
During Error
ATDE: Address
Transmitter During Err
7
6
5
4
3
2
1
0
Address Errors
ATCE: Addr Transmit
Ck Err
APE: Addr Parity Err
BAE: Bank Avail
Violation Err
LKTO: Bank Lock Timeout
NAE: NO ACK Err
RTCE: Read Transmit Ck Err
ACKTCE: ACK Transmit Ck Err
MMRE: Memory Mapping Reg Err
FNAE: Fatal No ACK Err
REQDE: Request Deassertion Err
UACKE: Unexpected ACK Err
ABTCE: Addr Bus Transmit Ck Err
BXB-0508-93
System Registers 7-7
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