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Table 7-32 Memory Channel Range Register Bit Definitions
Name
VALID
RSVD
BASE_ADR<38:20>
RSVD
INTLV_EN
ADR_EXTENT
Bit(s)
Type
Function
<31>
R/W, 0
Valid. When set, the contents of this register
are valid.
<30:27>
R/W, 0
Reserved. Read as zeros.
<26:8>
R/W, 0
Base Address <38:20>. The address of Mem-
ory Channel region. Aligned to the extent size.
<7:5>
R/W, 0
Reserved. Read as zeros.
<4>
R/W, 0
RM Interleave Enable. If set, the address
range for RM_RANGE_0 can only match if ad-
dress bit <6> is clear. The address range for
RM_RANGE_1 can only match if address bit
<6> is set. The range registers for channel 0
and channel 1 should be set to the same values.
<3:0>
R/W, 0
Address Extent. Address extent for Memory
Channel region.
<ADR_EXTENT>
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Memory Region Off Base
Address Enabled
1 Mbyte
2 Mbytes
4 Mbytes
8 Mbytes
16 Mbytes
32 Mbytes
64 Mbytes
128 Mbytes
256 Mbytes
512 Mbytes
1 Gbyte
2 Gbytes
4 Gbytes
8 Gbytes
16 Gbytes
32 Gbytes
System Registers 7-71
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