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Table 7-52 DDRn Register Bit Definitions (Continued)
Name
Bit(s)
<15>
EFLPD
<14>
EFLPC
<13:8>
DFLP
<7>
RSVD
CFLP
<6:4>
<3>
PAT
Type
Function
R/W, 0
Enable Flip Data Bit. When set in conjunction
with MDRA<AMEN>, the data bit selected in
DFLP<13:8> is flipped during memory write
transactions. This function allows diagnostics to
check ECC error detection logic.
NOTE: Setting both EFLPD and EFLPC results
in Uncorrectable ECC written into memory.
R/W, 0
Enable Flip ECC Check Bit. When set in con-
junction with MDRA<AMEN>, the check bit se-
lected in CFLP<6:4> will be flipped during mem-
ory write transactions. This function allows diag-
nostics to check ECC error detection logic.
NOTE: Setting both EFLPD and EFLPC results
in Uncorrectable ECC written into memory.
R/W, 0
Data Bit to Flip. This field contains a hexa-
decimal value of the data bit to flip within a
quadword during a memory write transaction
when bit <15> (EFLPD) of this register is set
and MDRA<AMEN> is set.
R0
Reserved. Reads as zero.
R/W, 0
Check Bit to Flip. This field contains a hexa-
decimal value of the check bit to flip within a
quadword during a memory write transaction
when bit <14> (EFLPC) of this register is set
and MDRA<AMEN> is set.
R/W, 0
Self-Test Pattern Select. When set, self-test
executes a defined data pattern required for the
"moving inversion" self-test mode of operation.
This bit in each of the four DDR registers and
MDRA<MMPS> must be set to execute this spe-
cial test mode.
System Registers 7-107
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