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assertion of this signal causes ICCNSE<DN_VRTX_ERRORn> to set. An
IPL 17 interrupt will also be posted if ICCNSE<INTR_NSES> is set.
When the down HDR completes processing of the failing packet, it at-
tempts to assert DECR_PKT<n> to the ICR gate array. DECR_PKT<n> is
only asserted if a packet was sent down the hose (for example, DMA read
return with error packet). This keeps the buffer counters in sync across
the two chips.
If the down Turbo Vortex packet contains an error that causes the down
HDR to discard the packet, then DECR_PKT<n> is not sent to the ICR. In
this case, a node reset (TLCNR<NRST>) is needed to resynchronize the
ICR and down HDR chips.
6.7.11 Miscellaneous I/O Port Errors
6.7.11.1 CSR Bus Parity Errors
The I/O port's internal CSR data path bus between IDR0 and the other
IDR and ICR gate arrays is protected by parity.
On CSR writes to I/O port registers, TLSB ECC is checked in IDR0. IDR0
also generates parity on the data to be transferred onto the I/O port's CSR
data bus. If the TLSB ECC check is without errors, then good parity is
generated for transmission onto the I/O port's CSR data bus. However, if
an uncorrectable ECC error is detected on the TLSB data, then bad parity
is transmitted onto the I/O port's CSR data bus. This results in one of the
IDPNSE<IDR_CSR_BUS_PE> or ICCNSE<ICR_CSR_BUS_PE> bits being
set, depending on whether the CSR to be written was in IDR1, IDR2,
IDR3, or ICR. The actual write of the CSR is blocked if an error is de-
tected on the write data.
On CSR reads of I/O port registers that are resident in either the ICR or
IDR1:3 parity is checked by IDR0. If no error is detected, then ECC is gen-
erated, and the data and ECC are transmitted onto the TLSB. However, if
a parity error is detected on the I/O port's CSR data bus, the CSR data cy-
cle is defaulted on the TLSB. This action results in TLBER-<DTDE>,
TLESR<PAR>, TLESR<TDE>, and IDPNSE0<IDR_CSR_BUS_PE> being
set.
6.7.11.2 Unexpected Mailbox Status Packet
This error typically indicates that the ICCNSE<MBX_TIP> bits were
cleared prior to a mailbox transaction reaching its timeout limit. When
this error condition is detected, the I/O port sets ICCNSE <UN_MBX_
STATn> and posts an IPL 17 interrupt if ICCNSE<INTR_NSES> is set.
Additionally, the ICR transmits a UTV_ERROR_A (or B) command across
the I/O port's internal command bus, which causes the up Turbo Vortex
transaction buffer pointers to be incremented to the next buffer.
6.7.11.3 ICR and IDR Internal Illogical Errors
If a catastrophic failure occurs within one of the gate arrays, an illogical
state may be encountered. If possible, either ICCNSE<ICR_IE> or ID-
PNSE<IDR_IE> is set to indicate the error. Additionally, the I/O port as-
I/O Port 6-77
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