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These registers can only hold information relative to one error. It is the
responsibility of software to read and clear all error bits and status. Even
when errors occur infrequently, there is a chance that a second error can
occur before software clears all status from a previous error. The error
register descriptions specify the behavior of the I/O port when multiple er-
rors occur.
The errors are prioritized as follows:
1.
2.
The I/O port overwrites status registers with data only if a higher priority
data error occurs. If software finds multiple data error bits set, the infor-
mation in the status registers reflects status for the highest priority error.
If multiple errors of the same priority occur, the information in the status
registers reflects the first error.
6.7.10 Hard I/O Port Errors
In addition to the error detection points already described, a number of
others have been implemented to provide a high degree of error detection
capability. These detection points consist primarily of the Up Hose inter-
face, the up and down Turbo Vortex interfaces, and the I/O port's internal
CSR data path bus between the gate arrays. The following sections docu-
ment the action taken by the I/O port in the presence of each group of er-
rors.
6.7.10.1 Up Hose Errors
If one of the up HDRs detects an error on an Up Hose packet, it discards
the packet and notifies the ICR chip that an error was detected. Addition-
ally, the up HDR toggles the hose decrement packet signal to indicate to
the I/O adapter that processing of the packet has been completed.
There is an error interface between the HDRs and the ICR. This interface
is used to notify the ICR chip that one of the following errors has occurred:
Reporting of Up Hose detected errors can be enabled by setting ICC-
NSE<INTR_NSES>, which results in the I/O port posting an IPL 17 inter-
rupt.
6.7.10.2 Up Turbo Vortex Errors
Error checking is implemented on the up Turbo Vortex interface in the
ICR gate array as well as the IDR gate array. Errors that are detected by
the ICR gate array prevent the transaction from being issued on the TLSB.
• The TLFADRn registers record the address, command, and bank num-
ber from the command.
FNAE, APE, BBE, or ATCE in TLBER register
NAE in TLBER register
• Parity error
• Packet error
• Overflow error
• Internal error
I/O Port 6-75
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