Dma Write Transactions - DEC AlphaServer 8200 Technical Manual

DMA IREAD command, the XMI I/O adapter acknowledges the IREAD
and pends the transaction. This frees the XMI for other bus traffic. The
XMI I/O adapter then transmits a quadword-aligned DMA IREAD request
packet to the I/O port on the Up Hose. Included in the DMA IREAD re-
quest packet is the target TLSB address, a tag field to allow the XMI I/O
adapter to associate the DMA IREAD request with the DMA return data
packet, and the length code indicating the amount of data requested.
After receiving the quadword-aligned DMA IREAD request packet, the I/O
port executes a Read Bank Lock command to TLSB memory at the target
address. This causes the TLSB memory to deassert and hold its
TLSB_BANK_AVL signal and return the requested data to the I/O port.
After the I/O port receives the read data from TLSB memory, it sets the
low-order bit of the addressed quadword and writes it back to memory us-
ing a Write Bank Unlock command. The Write Bank Unlock command
causes TLSB memory to assert its TLSB_BANK_AVL signal.
If this I/O port is node 8, the data is written back immediately using the
highest priority arbitration ID (TLSB_REQ8_HIGH) to minimize latency.
If not node 8, the I/O port uses TLSB_REQn, where n is the node number.
Atomicity is guaranteed by the Read Bank Lock/Write Bank Unlock TLSB
commands. The low-order bit of the addressed quadword indicates the
Lock status of the location. One equals Locked, zero equals Unlocked.
During the Write Bank Unlock cycle, the I/O port forces the low-order bit
of the addressed quadword to a one regardless of its original value.
If the Read-Modify-Write executed without errors, the I/O port transmits a
DMA read data return packet to the XMI adapter on the Down Hose. The
DMA read data return packet includes the tag from the corresponding
DMA IREAD request packet, the length code, an error bit indicating
whether or not the DMA IREAD request was successful, and the requested
data. Note that the I/O port returns the read data to the XMI I/O adapter
unmodified, even though it wrote the data back to memory with the low-
order bit forced to a one. That is, if the low-order bit was read as zero,
then it returns a zero. If the low-order bit was read as one, then it returns
a one. The XMI I/O adapter then transmits the data across the XMI to the
appropriate I/O device.
If no errors were detected, the DMA IREAD request transaction is com-
plete. If an error is detected on the Up Hose (for example, parity error or
sequence error), or if the TLSB bus Read-Modify-Write operation is unsuc-
cessful, the I/O port logs the error and generates an error interrupt to the
CPU(s).
Note that there is no special DMA write unlock request packet. The XMI
I/O device simply writes the low-order bit of the location to zero through a
generic DMA masked write request packet when it is ready to release the
lock.

6.3.6 DMA Write Transactions

When an I/O device requests a local I/O bus for a DMA write to memory,
the I/O bus adapter transmits a DMA write request packet to the I/O port
over the Up Hose. There are two types of DMA write request packets:
masked write and unmasked write. The main difference is that DMA
masked write packets require a Read-Modify-Write (one Read Bank Lock
and one Write Bank Unlock) operation on the TLSB bus and can be byte
masked by the I/O adapter, whereas a DMA unmasked write packet only
I/O Port 6-11