Table of Contents
Advertisement
onto the CSRCA bus during a read of one of its internal CSRs. During a
write command to one of the CTL's CSRs, a LD_EN signal from the se-
quencer is used to enable data from the CSRCA bus into the proper CSR.
Note that the LD_EN signal occurs on the last cycle of each of the four
data byte transfers.
5.3.1.3
CSR Multiplexing
The CTL contains two MUXes used to multiplex the appropriate CSR data
onto the CSRCA bus during a CSR read of an internal register. One MUX
is used to select the appropriate register currently being read. The select
for this MUX is determined by the CSRCA address, shown in Table 5-6.
The second MUX is used to select the appropriate byte of the 32-bit regis-
ter to be selected. This MUX is controlled by the MAI CSR sequencer.
5.3.1.4
CSRCA Parity
The CSRCA bus is protected by byte-wide odd parity. All data transmitted
through this bus is accompanied by a valid parity bit (CSRCA<8>) to be
checked against the data by all chips. Parity errors on the CSRCA bus
during CSR read transactions cause Unpredictable data to be returned to
the TLSB bus. Receiving data with bad ECC from the TLSB on CSR write
transactions causes the CSRCA parity bit to be inverted, forcing bad par-
ity. Any parity error that occurs on the CSRCA bus during a write dis-
ables that particular data byte from being written. Note that other data
bytes of the same register may have already been written.
5.3.2 MDI CSR Functions
Internally, each of the MDI chips consists of the following functional blocks
that take part in a TLSB CSR read or write operation of the memory mod-
ule:
5.3.2.1
MDI CSR Sequencer
The MDI CSR sequencer is the control mechanism that sequences the MDI
chip through a CSR read or a CSR write. Upon receiving a command from
the CTL, the MDI latches the command/address information into a regis-
ter. The reception of a command is the trigger for the MDI CSR sequencer
to begin its operation. Based on the command received on the CSRCA, one
of the chips drives the appropriate data onto the CSRCA bus. All four MDI
chips sequence through the nine clock cycles necessary to transfer four
data bytes across the CSRCA bus. Table 5-7 gives the criteria for which of
the chips drives the CSRCA bus during the nine data transfer cycles.
5-16 Memory Interface
• MDI CSR sequencer
• Merge register
• Multiplexing of local MDI CSRs and the data bytes within them
• Byte-wide parity generation and checking of the CSRCA bus
Advertisement
Table of Contents
