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Table 7-11 TLESRn Register Bit Definitions (Continued)
Name
Bit(s)
<16>
TDE
<15:8>
SYND1
SYND0
<7:0>
The four TLESRn registers are independent of each other. Each register
displays error and status information on one 64-bit slice of data. Two con-
secutive data cycles of the 64-bit data slice constitute one data transaction.
When an error is detected on the data bus, error bits may set in one or
more TLESRn registers.
Multiple error bits may be set from a single data transaction. For exam-
ple, <TCE> and <UECC> may both set at the same time. If <LOFSYN> is
not set, multiple error occurrences cumulatively set error bits. The <TDE>,
<SYND0>, and <SYND1> status bits present information from one data
transaction. The data transaction for which status is presented is the first
transaction that resulted in the most significant error type. The error
types, in order of significance, are:
1.
2.
3.
If a CRECC error occurs in one data transaction, then a CWECC error in
a later data transaction (and <LOFSYN> is not set), the <TDE>,
<SYND0>, and <SYND1> fields change to reflect the status at the time of
the CWECC error. If UECC is set, the status is latched and will not be
changed no matter how many other error bits set later. Software must
clear the error bits after each error to ensure proper reporting of the next
error.
The <TDE>, <SYND0>, and <SYND1> fields are not latched due to TCE or
DVTCE errors.
A zero syndrome is the expected no error condition. A nonzero ECC syn-
drome may indicate a single-bit or a multiple-bit error. A multiple-bit er-
ror syndrome results in a UECC error. A single-bit error syndrome results
in a CRECC or CWECC error (depending on command) for memory data.
Single-bit errors on memory data are soft errors and correctable. Not all
nodes, however, have the capability of correcting single-bit errors on CSR
data. If a node receives CSR data with a single-bit error syndrome and it
is not capable of correcting the data, a UECC error results.
7-28 System Registers
Type
Function
W1C, 0
Transmitter During Error. A status bit set when
data transmitted by a node results in error. This bit
is Undefined when <CRECC>, <CWECC>, and
<UECC> are zero.
R, U
Syndrome 1. Latched error syndrome from second
data cycle. This field is Undefined when <CRECC>,
<CWECC>, and <UECC> are zero.
R, U
Syndrome 0. Latched error syndrome from first
data cycle. This field is Undefined when <CRECC>,
<CWECC>, and <UECC> are zero.
UECC—Hard error
CWECC—Soft error during write command
CRECC—Soft error during read command
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