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Table 5-2
Two Strings—128MB/512MB Row/Column Address Bit Swapping
DRAM Type
No. of Banks
Interleaved
DRAM Address
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
10
Row_Adr<0>
Row_Adr<0>
11
12
Row_Adr<0>
13
Row_Adr<0>
14
Row_Adr<0>
15
Row_Adr<0>
16
Row_Adr<0>
Row_Adr<0>
x(21)
x(22)
Row_Adr<0>
21
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
17
Col_Adr<0>
18
Col_Adr<0>
Col_Adr<0>
19
20
Col_Adr<0>
Mod_Sel<0>
Mod_Sel<0>
Mod_Sel<0>
Bank_Sel<0>
Ras_Sel<0>
Ras_Sel<1>
Key to 4M DRAM Unused Row Addresses/Ras_Sel and Mod_Sel:
x(n) : Don't Care. (n) is the address bit driven even though it is not used by the DRAMs.
x : Don't Care. No address bits are involved in this decision.
"0" : Always 0. This signal is always held deasserted.
5.1.3.2
256MB/1024MB Memory Module Addressing
Table 5-3 shows how the TLSB addresses are allocated for a four-string
memory module. As shown, Ras_Sel<0> is now affected by addresses since
we need to select one of the two strings per bank (Ras_Sel<1> defaults to a
zero).
5-6 Memory Interface
4 Mbit
1
2
4
7
7
7
8
8
8
9
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
x(21)
x(21)
x(22)
x(22)
21
21
2
22
22
3
3
23
4
4
4
5
5
5
6
6
6
17
17
18
18
19
19
20
20
x
1
1
x
x
2
x
x
x
1
2
3
"0"
"0"
"0"
"0"
"0"
"0"
16 Mbit
8
1
2
7
7
7
8
8
8
9
9
9
10
10
10
11
11
11
12
12
12
13
13
13
14
14
14
15
15
15
16
16
16
x(21)
21
21
x(22)
22
22
21
23
23
22
2
24
23
3
3
24
4
4
5
5
5
6
6
6
17
17
17
18
18
18
19
19
19
20
20
20
1
x
1
2
x
x
3
x
x
4
1
2
"0"
"0"
"0"
"0"
"0"
"0"
4
8
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
21
21
22
22
23
23
24
24
25
25
4
26
5
5
6
6
17
17
18
18
19
19
20
20
1
1
2
2
x
3
3
4
"0"
"0"
"0"
"0"
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