Pci 0 And Pci 1 Interrupt Priority - DEC AlphaServer 8200 Technical Manual

rupt's vector and merging it with a programmable device IPL. The
INTR/IDENT is then sent to the HDR over the Up Hose.
Because the interrupt request lines of the devices are connected to more
than one of the HPC's 16 interrupt request input pins, software controls
the interrupt priority of the devices on each PCI bus. See Table 6-36.
Table 6-36 PCI 0 and PCI 1 Interrupt Priority
PCI 0 INT<15:0>L
PCI 0 INT<0>L
PCI 0 INT<1>L
PCI 0 INT<2>L
PCI 0 INT<3>L
PCI 0 INT<4>L
PCI 0 INT<5>L
PCI 0 INT<6>L
PCI 0 INT<7>L
PCI 0 INT<8>L
PCI 0 INT<9>L
PCI 0 INT<10>L
PCI 0 INT<11>L
PCI 0 INT<12>L
PCI 0 INT<13>L
PCI 0 INT<14>L
PCI 0 INT<15>L
All PCI device interrupts are issued as INTR/IDENTs at the same inter-
rupt priority level. No prioritization is provided between interrupts gener-
ated on different PCI buses. Normal Up Hose arbitration is used to select
the order in which HPCs issue INTR/IDENTs to the Up Hose. All HPCs
monitor the outstanding INTR/IDENTs and inhibit issuing INTR/IDENTs
at the outstanding IPLs until an interrupt status packet for that IPL is re-
turned on the Down Hose.
Device PCI 1 INT<15:0>L
SCSI 0 PCI 1 INT<0>L
SCSI 1 PCI 1 INT<1>L
Ethernet 0 PCI 1 INT<2>L
FDDI PCI 1 INT<3>L
SCSI 1 PCI 1 INT<4>L
Ethernet 0 PCI 1 INT<5>L
FDDI PCI 1 INT<6>L
SCSI 0 PCI 1 INT<7>L
Ethernet 0 PCI 1 INT<8>L
FDDI PCI 1 INT<9>L
SCSI 0 PCI 1 INT<10>L
SCSI 1 PCI 1 INT<11>L
FDDI PCI 1 INT<12>L
SCSI 0 PCI 1 INT<13>L
SCSI1 PCI 1 INT<14>L
Ethernet 0 PCI 1 INT<15>L
Device
SCSI 2
SCSI 3
Ethernet 1
NVRAM
SCSI 3
Ethernet 1
NVRAM
SCSI 2
Ethernet 1
NVRAM
SCSI 2
SCSI 3
NVRAM
SCSI 2
SCSI 3
Ethernet 1
I/O Port 6-85