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TLMBPR—Mailbox Pointer Registers
Address
BB + 0C00
Access
W
The TLMBPR register posts mailbox requests in an I/O port for ac-
cess to a CSR on an external I/O bus. Software access to this regis-
ter is through the single address BB+0C00. CPU hardware selects
one of the 16 registers by asserting the value of the CPU's virtual
ID on TLSB_BANK_NUM<3:0>.
6
3
RSVD
Table 7-14 TLMBPR Register Bit Definitions
Name
Bit(s)
RSVD
<63:40>
<39:6>
MBX_ADR
<5:0>
MBZ
Figure 7-1 shows the mailbox data structure.
7-32 System Registers
4
3
0
9
MBX_ADR <39:6>
Type
Function
W, 0
Reserved. Must be zero.
W, 0
Mailbox Address.
physical address of the mailbox data structure in
memory where the I/O port can find information to
complete the required operation.
W, 0
Reserved. Must be zero.
0
0
6
5
MBZ
BXB-0499-93
Contains the 64-byte aligned
0
0
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