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6.3.2 I/O Window Space Transactions
CSRs that exist on some external I/O buses are accessed through I/O win-
dow space transactions. One such external I/O bus is the PCI.
NOTE: Refer to the DWLPA PCI Adapter Technical Manual for further discus-
sion of transactions on the PCI bus and addressing of PCI devices.
When a CPU chip wants to read or write a location on one of these external
I/O buses, it issues a CSR read command or a CSR write command on the
TLSB, along with the address of the target location. The CPU chip also
asserts the data on the TLSB if the transaction is a write.
There are two types of direct I/O window space transactions:
Sparse address space transactions are used for byte size to quadword size
data transfers. The length of the transfer is controlled by a field in the
packet. Dense address space transactions are used for hexword size data
transfers only. Dense reads must always transfer eight longwords
(hexwords). Dense writes also transfer eight longwords, but include a
mask of valid longwords within the transfer.
The mapping between TLSB addresses and I/O bus addresses is dependent
on the I/O bus adapter. The hose protocol provides a packet field that can
be used to target different address spaces on the remote bus. This is used,
for example, on the PCI adapter to distinguish between PCI I/O, memory,
and configuration spaces.
Window space transactions need not be synchronous. The hose protocol
provides a flow control mechanism that prevents the I/O port from initiat-
ing more CSR protocol exchanges on the hose than the I/O bus adapter can
buffer. The I/O port has sufficient buffering to store up to four I/O window
transactions.
6.3.2.1
CSR Write Transactions to I/O Window Space
A CSR write command to node 4 through 8 I/O window space causes an
I/O port installed in that node to assemble a window write command
packet (sparse or dense, depending on the type of transaction) and trans-
mit it on the Down Hose. Flow control is maintained by Window Space
Decrement Queue Counter registers (TLWSDQRn) in each CPU node.
Each CPU node increments its associated I/O Queue Counter register
whenever it detects an I/O window transaction on the TLSB.
When the I/O port empties the window write command packet from its in-
ternal buffer, it issues a CSR write command to the TLWSDQR register in
CSR broadcast space. This causes each CPU node to decrement its associ-
ated TLWSDQR register. The I/O port does not ACK the write broadcast
nor generate the associated data cycles. The I/O port then transmits the
window write command packet on the Down Hose and increments its re-
mote adapter node buffer counters.
When the I/O port receives a window CSR Write Status Return packet on
the Up Hose, it decrements its remote adapter node buffer counters and
discards the packet.
• Sparse address space
• Dense address space
I/O Port 6-7
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