Decchip 21164 Processor; Cpu Module Simple Block Diagram - DEC AlphaServer 8200 Technical Manual

Figure 3-1

CPU Module Simple Block Diagram

3.1.1 DECchip 21164 Processor

The DECchip 21164 microprocessor is a CMOS-5 (0.5 micron) superscalar,
superpipelined implementation of the Alpha architecture.
DECchip 21164 features:
3-2 CPU Module
21164A
Cache
Data Buffer
DIGA DIGA
• Alpha instructions to support byte, word, longword, quadword, DEC
F_floating, G_floating, and IEEE S_floating and T_floating data types.
It provides limited support for DEC D_floating operations.
• Demand-paged memory mangement unit which, in conjunction with
PALcode, fully implements the Alpha memory management architec-
ture appropriate to the operating system running on the processor.
The translation buffer can be used with alternative PALcode to imple-
ment a variety of page table structures and translation algorithms.
• On-chip 48-entry I-stream translation buffer and 64-entry D-stream
translation buffer in which each entry maps one 8-Kbyte page or a
group of 8, 64, or 512 8-Kbyte pages, with the size of each translation
buffer entry's group specified by hint bits stored in the entry.
• Low average cycles per instruction (CPI). The DECchip 21164 can is-
sue four Alpha instructions in a single cycle, thereby minimizing the
average CPI. A number of low-latency and/or high-throughput fea-
tures in the instruction issue unit and the on-chip components of the
memory subsystem further reduce the average CPI.
• On-chip high-throughput floating-point units capable of executing both
Digital and IEEE floating-point data types.
21164A
Cache
MMG
Data Buffer
ADG DIGA DIGA
TLSB Bus
BXB0825.AI