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A2MAPE1, 7-61
B
Backup cache, 1-4, 4-2
BAE, 7-12
BANKV, 7-24
Bank address decoding, 2-9
Bank available flags, 5-4
Bank available status, 2-11
Bank available transition, 2-14
Bank busy check, 2-6
Bank busy violation, 6-71
Bank Busy Violation Error bit, 7-12
Bank collision, 2-15
Bank collision effect on priority, 6-34
Bank contention, CSR, 2-15
Bank decode in memory, 2-6
Bank lock and unlock, 2-15
Bank Lock Timeout bit, 7-11
Bank Lock Timeout Disable bit, 7-17
Bank match logic, 5-3
Bank Valid bit, 7-24
Base addresses, node space, 7-3
Base addresses, TLSB nodes, 2-28
BASE_ADR<38:20>, 7-71, 7-111
BAT, 7-90
Battery Disable bit, 7-90
Battery Disconnected bit, 7-90
Battery OK bit, 7-90
Battery Reenable bit, 7-90
BCACHE_SIZE, 7-53
BCIDLETIM, 7-53
BDC, 7-90
BDIS, 7-90
Block diagram
CPU module, 3-2
I/O port, 6-3
I/O subsystem, 6-1
KTFIA, 6-79
memory module, 4-10
BQ_MAX_ENT, 7-53
BREN, 7-90
BRFSH, 7-98
Burst Refresh bit, 7-98
Bus architecture, 1-2
Bus commands, address, 2-17
Bus cycles, 2-16
Bus Error register, 7-7
Bus Queue Maximum Entries bits, 7-53
Bus request, 2-13
Bus sequencing, 2-11
Bus signals, miscellaneous, 2-24
Bus transaction initiation, 2-12
Byte mask field, 6-51
B-cache, 3-4, 4-2
Index-2
states, 4-4
state changes, 4-5
B-Cache Idle Time bits, 7-53
B-Cache Size bit, 7-53
B-Cache Size bits, 7-80
B-cache states, 4-4
B-cache tags, 4-3
C
Cache
backup, 4-2
data, 4-1
instruction, 4-1
internal, 4-1
second level, 4-2
state transition, 4-5, 4-6
Cache coherency, 4-2
Cache coherency on processor writes, 4-8
Cache coherency protocol, 2-2
Cache index mapping, 4-3
Cache Queue Maximum Entries bits, 7-53
Cache tag lookup, 2-6
Cache tag mapping, 4-3
Cache, backup, 1-4
CACSIZ, 7-80
CDER, 7-108
CFLP, 7-107
Check Bit to Flip bits, 7-107
Clear Self-Test Data Error Registers bit, 7-108
CMD, 7-33
CMDV, 7-24
Coherency protocol, cache, 2-2
Collision, bank, 2-15
Commands, address bus, 2-17
Command acknowledge, 2-16
Command field parity errors, 3-17
Command Valid bit, 7-24
Configuration, 1-1
Configuration register, 7-14
Configuration, I/O, 6-2
Console, 3-4
Console Communications register, 7-68
Console firmware, 1-6
Console support hardware, 1-4
Console Winner CPU0 Read bit, 7-80
Console Winner CPU0 Write bit, 7-81
Console Winner CPU1 Read bit, 7-80
Console Winner CPU1 Write bit, 7-81
Control address interface, 4-11, 5-1
Control logic, hose, 6-82
Conventions, register, 7-1
CONWIN0R, 7-80
CONWIN0W, 7-81
CONWIN1R, 7-80
CONWIN1W, 7-81
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