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Mailbox Command Packet
The Mailbox Command packet is used by processors to access control and
status registers in adapters on the XMI and Futurebus+.
Status for the Mailbox Command packet is returned in a separate packet
on the Up Hose called a Mailbox Status Return packet.
Only one Mailbox Command packet can be issued at a time by the I/O port,
regardless of the Down Hose for which it is destined. A Mailbox Status
Return packet must be sent on the Up Hose (for the currently outstanding
Mailbox Command packet) before the I/O port can issue another Mailbox
Command packet down any hose.
All Mailbox Command packets that are writes can be byte masked. Any
combination of mask bits is allowed by the Down Hose. However, the I/O
bus adapter may or may not support this capability. The mask bits are
Mask Disable bits as defined in the Alpha SRM and, therefore, writing
them to a 1 disables the byte from being written. Refer to the Alpha SRM
for more information on the mailbox structure in memory.
The Mailbox Command packet is supported by the Mailbox Only, I/O Win-
dow, Full, and Memory Channel variants of the hose protocol.
Figure 6-14 shows the Mailbox Command packet.
Figure 6-14
Mailbox Command Packet
Clock
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
1
Bus (Hose number)
2
3
4
5
6
7
8
Table 6-15 gives the description of the Mailbox Command packet.
DND<31:0>
CMD<31:14>
I/O Target Address <31:0>
I/O Target Address <63:32>
Write Data <31:0>
Write Data <63:32>
8
1 0
CMD<11:0>
MBZ
MBZ
MBZ
7
6
5
4
3
2
1
0
Mask
BXB0809.AI
I/O Port 6-41
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