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Correctable Read Data Error bit, 7-9
Correctable Read Data Error Interrupt Disable
bit, 7-18
Correctable Read ECC Error bit, 7-27
Correctable Write Data Error bit, 7-9
Correctable Write Data Error Interrupt
Disable bit, 7-18
Correctable Write ECC Error bit, 7-27
CPU Halt Enable bit, 7-64
CPU Identification bit, 7-73
CPU Interrupt Mask register, 7-31
CPU interrupt rules, 8-2
CPU Mask bits, 7-31
CPU module address space, 3-6
CPU module block diagram, 3-2
CPU module components, 3-1
CPU Module Configuration register, 7-52
CPU module errors
faults, 3-15
hard errors, 3-14
nonacknowledged CSR reads, 3-16
soft errors, 3-14
CPU module interrupts, 8-6
CPU module registers, 7-44, 7-45
CPU module wrapping, 3-7
CPU module, overview, 1-3
CPU Number bit, 7-77
CPU Pipe Disable bit, 7-52
CPU to MMG Addr Par Err #0, 7-56
CPU to MMG Addr Par Err #1, 7-56
CPU virtual ID, 6-15
CPU 0 bit, 7-27
CPU 1 bit, 7-27
CPU0, 7-27
CPU0 Disable bit, 7-53
CPU0_DIS, 7-53
CPU1, 7-27
CPU1 Disable bit, 7-53
CPU1_DIS, 7-53
CPU_ID, 7-73
CPU_MASK, 7-31
CPU_NUM, 7-77
CPU_PIPE_DIS, 7-52
CQ_MAX_ENT, 7-53
CRDD, 7-18
CRDE, 7-9
CRECC, 7-27
CSRCA addressing, 5-15
CSRCA encoding, 5-14
CSRCA parity, 5-16, 5-18
CSR addressing, 2-25
CSR addressing scheme, 2-8
CSR address bit mapping, 2-26
CSR address mapping, 2-29
CSR address space map, 2-27
CSR address space regions, 2-26
CSR bank contention, 2-15
CSR bus parity errors, 6-77
CSR interface context, 5-13
CSR interface, memory, 5-13
CSR multiplexing, memory, 5-16, 5-17
CSR reads to remote I/O, 2-32
CSR read data ECC, 5-11
CSR Read Data Return Data register, 7-41
CSR Read Data Return Error register, 7-42
CSR read transactions, I/O window space, 6-8
CSR state machine, 5-2
CSR transactions, 6-84
CSR writes to remote I/O, 2-32
CSR write data ECC check, 5-10
CSR Write Not Transmitted bit, 7-55
CSR write transactions, I/O window space, 6-7
CSR_WR_NXM, 7-55
CTL CSR functions, 5-13
Ctrl/P Halt bit, 7-66
Ctrl/P Halt Enable bit, 7-64
Ctrl/P_HALT, 7-66
Ctrl/P_HALT_ENA, 7-64
CWDD, 7-18
CWDE, 7-9
CWDE2, 7-9
CWECC, 7-27
Cycles per instruction, 3-2
Cycles, address bus, 2-16
D
Data Bit to Flip bits, 7-107
Data bus concepts, 2-18
Data bus errors, 3-18, 6-72
data status errors, 2-41
double-bit ECC errors, 2-40
illegal sequence errors, 2-40
multiple errors, 2-41
SEND_DATA timeout errors, 2-40
single-bit ECC errors, 2-40
transmit check errors, 2-41
Data bus errors, summary, 2-42
Data bus sequencing, 2-18
Data cache, 4-1
Data Control Transmit Check Error bit, 7-8
Data Diagnostic register, 7-106
Data field, 2-20
Data Movement Done bit, 7-73
Data Movement in Progress bit, 7-73
Data Mover Command bits, 7-74
Data Mover Command register, 7-72
Data Mover Command Valid bit, 7-73
Data Mover Destination Address register, 7-76
Data Mover Source Address register, 7-75
Data path logic, 5-9
Data Read from Remote CSR bits, 7-41
Index-3
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