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Four error bits in the TLBER register will set as a result of the five error
bits in this register.
• CRECC sets TLBER<CRDE>
• CWECC sets TLBER<CWDE>
• UECC sets TLBER<UDE>
• TCE, when no ECC error detected, sets TLBER<FDTCE>
• DVTCE sets TLBER<CRDE> during a read command
• DVTCE sets TLBER<CWDE> during a write command
If multiple error bits set in one TLESRn register during a single data
transaction, for UECC in one data cycle and CRECC in the other, the most
significant corresponding error bit in the TLBER register (<UDE>) must
set. It is not necessary that two bits set in the TLBER register. This is
implementation dependent.
If error bits set in two TLESRn registers during a single data transaction,
for example, <UECC> in TLESR0 and <CRECC> in TLESR1, the most sig-
nificant corresponding error bit in the TLBER register (<UDE>) must set.
It is not necessary that two bits set in the TLBER register. This is imple-
mentation dependent.
The TLBER register also records which TLESRn registers contain status
for the most significant error by setting the <DSn> bits accordingly. All
<DSn> bits are overwritten when an error of higher significance occurs.
<DSn> bits are set only for the TLESRn registers that detect the error of
highest significance. If <UECC> is set in TLESR0 and <CRECC> in
TLESR1, only <DS0> sets in the TLBER register. Should a UECC error be
detected later in the TLESR1 register, <SYND0> and <SYND1> are over-
written and no longer correspond to the first occurrence of CRECC in the
TLBER register.
This register is locked when the first error bit gets set in this register if
<LOFSYN> is set. The error bits <CRECC>, <CWECC>, <UECC>,
<DVTCE>, and <TCE> cause the register to be locked. When the register
is locked, no bits change value until all error bits are cleared by software
or <LOFSYN> is cleared. Locking the register is intended only for diag-
nostics. It is not intended for use in normal operation.
System Registers 7-29
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