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Table 4-1
B-Cache States
B-Stat
V
S
D
State of Cache Line Assuming Tag Match
0 X
X
Cache miss. The block is not present in the cache.
Valid for read or write. This cache line contains the only cached copy of the
1 0
0
block. The copy in memory is identical to this block.
Valid for read or write. This cache line contains the only cached copy of the
1 0
1
block. The contents of the block have been modified more recently than the
copy in memory.
Valid block. Writes must be broadcast on the bus. This cache block may also
1
1
0
be present in the cache of another CPU. The copy in memory is identical to
this block.
Valid block. Writes must be broadcast on the bus. This cache line may also be
1
1
1
present in the cache of another CPU. The contents of the block have been
modified more recently than the copy in memory.
A block becomes valid when the block is allocated during a fill. A block be-
comes invalid when it is invalidated due to a write on the bus by some
other processor.
A block becomes shared when a DTag lookup (due to a TLSB read)
matches. The ADG informs the appropriate DECchip 21164 to set the B-
cache tag Shared bit. A block becomes unshared when a Write Block is is-
sued by the DECchip 21164. TLSB writes always leave the block valid, not
shared, not dirty in the cache of the originator, and invalid in all other
caches. In the event of a write to Memory Channel space that gets re-
turned a shared status, the CPU module initiating the write causes the
block to transition back to the Shared state in the initiating CPU's cache
and in the DTag.
A block becomes dirty when DECchip 21164 writes an unshared block. A
block becomes clean when that data is written back to memory. TLSB
memory accepts updates on writes or victims, but not on reads, so reads do
not cause the dirty bit to be cleared.
If a block is dirty, and is being evicted (because another block is being
read in to the same B-cache index), the swapped out block is referred to as
a victim. The CPU module allows for one victim at a time from each of the
two CPUs.
4.2.6 B-Cache State Changes
The state of any given cache line in the B-cache is affected by both proces-
sor actions and actions of other nodes on the TLSB.
• State transition due to processor activity
Table 4-2 shows the processor and bus actions taken in response to a
processor B-cache tag probe. Match indicates that the tag address com-
parison indicated a match.
Memory Subsystem 4-5
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